Senior Digital Mixed Signal DV Engineer

Texas Instruments; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading technology firm in Bangalore is seeking a Senior Analog Mixed-Signal Verification Engineer to develop verification plans and create high-fidelity analog models. Candidates should have at least 3 years of experience in mixed-signal design verification and a degree in Electrical Engineering or Electronics. Proficiency in Cadence tools and strong communication skills are a must. The company promotes a diverse and inclusive work environment.

Qualifications

• Minimum 3 years of hands-on experience in Analog Mixed-Signal design verification.
• Proficiency in analog behavioural modelling using Verilog-AMS, Verilog-A, or Wreal.
• Direct experience with mixed-signal verification involving a combination of schematic, behavioural models, and RTL.

Responsibilities

• Develop detailed coverage-driven Verification Plans by collaborating closely with teams.
• Create high-fidelity analog behavioural models for efficient top-level simulation.
• Work with teams to debug complex issues and ensure successful product delivery.

Skills

Analog behavioural modelling

Mixed-signal verification

Communication skills

Scripting

Education

Bachelor’s or Master’s degree in Electrical Engineering or Electronics and Communication Engineering

Tools

Cadence Virtuoso/AMS Designer

Job description

Senior Analog Mixed-Signal (AMS) Verification Engineer

Location: Bangalore, India

Experience: 3–10 Years

What will you be doing in this role?

• Verification Strategy: Develop detailed coverage-driven Verification Plans by collaborating closely with System, Application, and Design teams.
• Modelling & Simulation: Create high-fidelity analog behavioural models using Verilog-A, Verilog-AMS, Wreal (RNM) or EENet to enable efficient top-level simulation.
• Environment Development: Build and enhance mixed signal testbenches using a combination of schematic, models, and RTL.
• Checkers & Assertions: Implement real-time analog checkers and post-processing checker strategies to ensure functional correctness.
• Full-Cycle Verification: Execute RTL and Gate Level Simulations (GLS), running regressions and tracking functional coverage goals until tape-out.
• Collaboration: Work with Digital DV, Analog Designers, and Post-Silicon Validation teams to debug complex issues and ensure successful product delivery.

Basic Requirements (Must-Haves)

• Education: Bachelor’s or Master’s degree in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE)
• Experience: Minimum 3 years of hands‑on experience in Analog Mixed‑Signal (AMS) design verification.
• Modelling Skills: Proficiency in analog behavioural modelling using Verilog-AMS, Verilog-A, or Wreal.
• Verification Flow: Direct experience with mixed‑signal verification involving a combination of schematic, behavioural models, and RTL.
• Tool: Strong command of Cadence Virtuoso/AMS Designer toolsets and debug environments or other standard mixed‑signal simulation tools.
• Communication: Clear ability to present technical analysis and conclusions to internal stakeholders and business leaders.

Preferred Skills & "Good to Have" (Innovation & Automation)

• Advanced DV: Knowledge of SystemVerilog (SV) and UVM.
• Automation: Proficiency in scripting (Python, Perl, or Shell) to automate simulation flows and data analysis; interest in AI‑driven verification methodologies.
• Domain Expertise: Experience in signal processing, PMICs, or high‑speed communication interfaces.
• Silicon Interaction: Experience in silicon debug and working alongside silicon validation teams.
• Standard protocols exposure: Verification experience with I2C, SPI, UART, ASI, etc.

ECL/GTC Required

Yes

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment.