AMS Verification engineer

Cyient; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Cyient in Hyderabad seeks an experienced AMS Verification engineer to verify analog mixed-signal IPs and system-level interfaces. You will contribute to the development of verification environments using SystemVerilog, UVM and Verilog-AMS/Verilog-A in collaboration with SoC teams.

We expect hands-on experience with Cadence Xcelium, AMS Designer, Synopsys VCS AMS, and Siemens Questa ADMS, plus scripting in Python/TCL for test automation and regression management.

Qualifications

• Bachelor's or master's degree in ECE or EE.
• 3–5 years of AMS Verification experience.
• Strong understanding of Analog Mixed-Signal design and verification.
• Hands-on experience with SystemVerilog, UVM, Verilog-AMS/Verilog-A.
• Experience with simulators: Cadence Xcelium, Cadence AMS Designer, Synopsys VCS AMS, Siemens Questa ADMS.
• Strong debugging and problem-solving skills.
• Experience in scripting with Python, Perl, Shell, or TCL.
• Good understanding of assertions, coverage concepts, and regression management.

Skills

SystemVerilog

UVM

Verilog-AMS

Verilog-A

Mixed-signal verification

Debugging

Python

Perl

Shell

TCL

Assertions

Coverage concepts

Regression management

Education

Bachelor's/Master's degree in Electronics & Communication Engineering or Electrical Engineering

Tools

Cadence Xcelium

Cadence AMS Designer

Synopsys VCS AMS

Siemens Questa ADMS

Job description

• Bachelor's/Master's degree in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-5 years of experience in AMS Verification.
• Strong understanding of Analog Mixed-Signal design and verification concepts.
• Hands-on experience with:
  • SystemVerilog
  • UVM
  • Verilog-AMS / Verilog-A
  • Mixed-signal verification methodologies
• Experience with simulators such as:
  • Cadence Xcelium
  • Cadence AMS Designer
  • Synopsys VCS AMS
  • Siemens Questa ADMS
• Strong debugging and problem-solving skills.
• Experience in scripting using Python, Perl, Shell, or TCL.
• Good understanding of assertions, coverage concepts, and regression management.

Preferred Skills

• Experience in verifying high-speed interfaces, ADC/DACs, PLLs, SerDes, PMICs, or Sensor IPs.
• Familiarity with real-number modeling (RNM).
• Knowledge of AMS verification acceleration techniques.
• Experience with SoC-level integration and verification.
• Understanding of low-power verification concepts.