Design Verification Engineer (Analog/Mixed-Signal Team)

MediaTek; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

MediaTek is seeking an experienced Analog/Mixed-Signal Functional Verification engineer to drive AMS IP verification for SERDES, sensors, and beyond. You will collaborate with digital and analog design teams, apply and advance DV methodologies, and support the entire AMS verification lifecycle from spec to coverage closure and post-silicon debugging.

The role requires hands-on verification of ASICs with UVM-based environments, strong Verilog/SystemVerilog and SVA skills, and experience with test

Qualifications

• 3+ years ASIC functional verification hands-on experience.

Responsibilities

• Work in AMS IP Design Verification, in UVM-based verification environment.
• Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.

Skills

UVM

Verilog/SystemVerilog

SVA

DV tools & testbench

C/Python scripting

AMS IP experience

SerDES IP experience

Analog mixed-signal fundamentals

Gate-level simulations

Version control (Perforce/Plastic)

Tools

Perforce

ClearCase

Makefile

Job description

Work on Analog/Mixed-Signal Functional Verification for Analog/Mixed-Signal IPs, such as SERDES, Sensors and beyond. The candidate will work with digital design, analog design, analog behavioral modeling and other design verification teams, apply and advance existing and evolving Digital and AMS Verification methodologies and processes, and contribute to the entire life cycle of AMS Functional Verification process, from understanding specification, test planning to coverage closure and post silicon debugging support, to ensure High Quality and High Efficiency of Pre-Si Verification Delivery towards high quality silicon products.

Skills/Experience

• Quick learner with strong critical thinking and creative problem-solving skills.
• Solid knowledge in ASIC design process, digital design, and UVM-based design verification methodologies.
• Proficient on using design and verification languages: UVM, Verilog, System Verilog, and System Verilog Assertions (SVA).
• Proficient on Design Verification tools and techniques, including test bench development, simulation, debugging and coverage closure, etc.
• Knowledge on Design Verification development process, from specification to test plan, to configurable test bench, drivers, and checkers development, to test suite building to meet functional and code coverage goals,
• 3+ years ASIC functional verification hands-on work experience, preferably with some verification experience on analog mixed signal IPs or SERDES IPs, such as USB, UFS, PCIe, DDR-PHY, etc.
• Power-aware simulations and gate level simulations is a plus.
• Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., Perforce, ClearCase, etc.) is a plus.
• Knowledge of Analog Mixed-Signal Design Fundamentals and analog behavioral modeling is a plus.
• Familiar with programming languages: C, C++, and/or SystemC is a plus.

Responsibilities

• Work in AMS IP Design Verification, in UVM-based verification environment.
• Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals
• Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures.
• Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support.
• Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.