Senior AMS Verification Engineer

Best NanoTech; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Best NanoTech in Bengaluru is seeking Analog Mixed-Signal (AMS) Verification Engineers with 3+ years experience to work on complex analog/mixed-signal IP verification, including ADC/DAC/PLL blocks, using Verilog-AMS and RNM.

Candidates will leverage Cadence mixed-signal environment (Virtuoso, ADE Assembler, Xcelium) to develop verification strategies, create models, debug, and ensure coverage while collaborating with analog designers.

Qualifications

• 3+ years of hands-on AMS verification experience.
• Strong fundamentals in analog and mixed-signal design.
• Experience with Verilog-AMS and Real Number Modeling (RNM).
• Proficient in verification of ADC, DAC and PLL blocks.
• Experience with Cadence mixed-signal simulation and verification tools.

Responsibilities

• Develop and execute verification strategies for Analog Mixed-Signal designs.
• Create and maintain Analog Mixed-Signal behavioral models using Verilog-AMS.
• Develop and validate RNMs for analog/mixed-signal blocks.
• Perform functional verification of ADC, DAC, PLL and other MS IPs.
• Develop verification environments and test scenarios for AMS functionality.
• Work with Cadence Virtuoso, ADE Assembler and Xcelium for simulation and verification.
• Perform detailed mixed-signal waveform analysis and debugging.
• Analyze simulation failures and identify design, modeling or verification issues.
• Perform verification coverage analysis and identify coverage gaps.
• Collaborate with analog designers to resolve issues and maintain regression environments.

Skills

Verilog-AMS

RNM

AMS fundamentals

Education

BE/BTech in Electronics

Tools

Cadence Virtuoso

ADE Assembler

Xcelium

Job description

Experience: 3+ years relevant experience in AMS Verification

Role Overview

We are hiring Analog Mixed-Signal (AMS) Verification Engineers for semiconductor design and verification assignments involving complex analog and mixed-signal IPs. The role requires strong fundamentals in mixed-signal design, hands‑on experience with Verilog-AMS and Real Number Modeling (RNM), and expertise in verification and debugging of blocks such as ADC, DAC and PLL.

Candidates should have practical experience with the Cadence mixed-signal verification environment, including Virtuoso, ADE Assembler and Xcelium.

Key Responsibilities

• Develop and execute verification strategies for Analog Mixed-Signal (AMS) designs.
• Create and maintain Analog Mixed-Signal behavioral models using Verilog-AMS.
• Develop and validate Real Number Models (RNM) for analog and mixed-signal blocks.
• Perform functional verification of ADC, DAC, PLL and other mixed-signal IPs.
• Develop verification environments and test scenarios for analog/mixed-signal functionality.
• Work with Cadence Virtuoso, ADE Assembler and Xcelium for simulation and verification.
• Perform detailed mixed-signal waveform analysis and debugging.
• Analyze simulation failures and identify design, modeling or verification issues.
• Perform verification coverage analysis and identify coverage gaps.
• Work closely with analog designers and verification engineers to resolve functional issues.
• Maintain verification models, test cases and regression environments.
• Support verification closure through debugging, regression analysis and coverage review.

Required Qualifications

• B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical Engineering, VLSI, Microelectronics or a related discipline.
• Minimum 3 years of relevant hands‑on AMS Verification experience.
• Strong understanding of analog and mixed-signal design fundamentals.
• Good understanding of common analog building blocks and their behavior.
• Hands‑on experience with Verilog-AMS and Real Number Modeling.
• Practical experience in verification of ADC, DAC, PLL and mixed‑signal blocks.
• Experience with Cadence mixed‑signal simulation and verification tools.