Memory Layout Engineer

Digicomm Semiconductor INC; Bengaluru, Pune District, Hyderabad, Dadri; On-site; INR 600,000 - 900,000; Full time

Job summary

Digicomm Semiconductor INC is seeking a skilled engineer to work on memory compiler development and layout optimization in Bengaluru. The role involves addressing routing congestion, performing physical verification, and applying analog layout techniques to improve speed, power, noise, and area.

You will use Cadence and Mentor tools in a Linux environment and mentor junior team members. Ideal candidates will have a BTech/MTech and strong leadership and communication skills, with hands-on

Qualifications

• BTech or MTech in Electronics/ECAD related field
• Experience or strong interest in memory compilers and layout optimization
• Strong knowledge of routing congestion and physical verification in layout
• Experience with DRC/LVS/ERC, antenna issues, and DFM checks
• Familiar with analog layout techniques and circuit principles affected by layout
• Proficiency with Cadence/Mentor tools in a Linux environment; VirtuosoXL power user
• Leadership and mentoring abilities; clear communication and proactive teamwork

Responsibilities

• Develop memory compilers and address layout-related issues to optimize performance.
• Lead and mentor layout team members; review outputs for quality and delivery.
• Perform or guide verification checks (DRC/LVS/ERC/Antenna/DFM).
• Apply knowledge of analog layout techniques to optimize speed, power, noise, and area.
• Use Cadence/Mentor tools on Linux; ensure efficient tool usage and workflow.
• Communicate effectively and proactively coordinate with team members.

Skills

Memory compiler development

Layout optimization

Routing congestion

Physical verification

DRC/LVS/ERC/Antenna/DFM

Analog layout techniques

Circuit principles awareness

Leadership & mentoring

Education

BTECH/MTECH

Tools

Cadence

Mentor Graphics

VirtuosoXL

Job description

• Qualifications : BTECH/MTECH

Job Description

• Experience or strong interest in developing memory compilers, addressing layout-related issues, and ensuring optimization.
• Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout.
• Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
• Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area.
• Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL.
• Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery Excellent communication skills and proactive at work.
• Excellent communication skills and proactive at work