Lead /Senior Design Verification Engineer

BITSILICA; Hyderabad; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

BITSILICA is seeking hands-on ASIC verification engineers with 4+ years experience focused on PCIe, DDR, Ethernet and CXL protocols. Candidates will build verification environments from scratch using SystemVerilog and UVM, develop test plans and test benches, and write test cases for IP/Subsystem/SOC verification.

The role requires proficiency in C/C++, Perl, Tcl and experience with major simulators (Cadence, Mentor, Synopsys).

Qualifications

• 4+ years of hands-on verification experience with PCIe, DDR, Ethernet and CXL protocols.
• Experience in IP/Subsystem/SOC ASIC Verification.
• Hands-on on test plan and test bench development.
• Proficient in writing test cases, simulation and debugging.
• Experience building verification environments from scratch using SystemVerilog and UVM.
• Must work on PCIe/Eth/USB/DDR/AXI technologies.
• Experience with Cadence, Mentor or Synopsys simulators.
• Strong OO programming skills in C, C++, Perl, Tcl.

Responsibilities

• Develop and execute test plans and test benches for ASIC verification.
• Verify IP/Subsystem/SOC components with a focus on PCIe, DDR, Ethernet and CXL.
• Write and debug test cases; perform simulations and waveform analysis.
• Build and maintain verification environments using SystemVerilog and UVM.
• Collaborate to ensure verification coverage across PCIe, Ethernet, DDR and related interfaces.

Skills

PCIe verification

DDR verification

Ethernet verification

CXL verification

SystemVerilog

UVM

Test bench development

C/C++

Perl

Tcl

Education

Bachelor's or Master's degree in Electronics, VLSI, or Embedded Systems

Tools

Cadence

Mentor Graphics

Synopsys

SystemVerilog

Job description

Experience: We are seeking individuals with 4 or more years of hands-on verification experience, with a primary focus on PCIe, DDR, ETHERNET, and CXL protocols.

Job Description:

• Experience in IP/Subsystem/SOC ASIC Verification.
• Hands-on expertise of working on Test Plan & Test bench development.
• Proficient in writing test cases, simulation and debugging.
• Experience in building Verification Environment from scratch using System-Verilog and methodologies like UVM.
• Experience in developing Test Plan and Test Cases
• Hands on work experience on any of PCIe/Eth/USB/DDR/AXI etc
• Experience With One Or more simulators from the major EDA suppliers (Cadence, Mentor Or Synopsys)
• Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, Tcl.

Qualification: We require candidates with a Bachelor's or Master's degree in Electronics, VLSI, or Embedded Systems.