Design and Verification Engineer

Lyptus Technologies; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Lyptus Technologies seeks an experienced Design Verification Engineer to lead systemVerilog/UVM verification for ASIC/SoC IPs. Strong hands-on expertise in PCIe protocols and high-speed interfaces is required.

You will develop verification environments, test plans, and coverage metrics while collaborating with RTL teams to ensure sign-off on releases. The role emphasizes regression, debugging, and reusable verification components, with a focus on pre-silicon verification methodologies and

Qualifications

• Strong hands-on SystemVerilog/UVM verification experience.
• Experience in pre-silicon verification of ASIC/SoC/IP.
• Proficient in PCIe protocol verification and debugging.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments.
• Create test plans, test scenarios, test cases, sequences, scoreboards, monitors, and checkers.
• Perform functional and constrained-random verification of IPs, subsystems, and SoCs.
• Verify high-speed protocols with PCIe experience.
• Debug RTL and simulation failures using waveform analysis and debugging tools.
• Develop and monitor functional and code coverage and drive closure.
• Write and debug SystemVerilog Assertions (SVA).
• Participate in regression execution, failure analysis, and verification sign-off.
• Collaborate with RTL designers to resolve functional issues.
• Contribute to verification methodology, reusable components, and automation.

Skills

SystemVerilog

UVM

ASIC/SoC/IP verification

PCIe protocol verification

RTL debugging

SystemVerilog Assertions (SVA)

constrained-random verification

functional coverage

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI

Tools

VCS

Xcelium

Questa

Job description

Design Verification Engineer VLSI

Job Location: Bangalore
Experience: 6 - 15 Years
Employment Type: Full-time

Job Summary

We are looking for an experienced Design Verification Engineer with strong hands-on experience in SystemVerilog, UVM, and protocol/IP verification. The candidate should have good experience in pre-silicon verification of ASIC/SoC/IP and strong debugging skills.

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments.


• Create test plans, test scenarios, test cases, sequences, scoreboards, monitors, and checkers.


• Perform functional and constrained-random verification of IPs, subsystems, and SoCs.


• Verify high-speed protocols, with strong preference for PCIe experience.


• Debug RTL and simulation failures using waveform analysis and debugging tools.


• Develop and monitor functional and code coverage and drive coverage closure.


• Write and debug SystemVerilog Assertions (SVA).


• Participate in regression execution, failure analysis, and verification sign-off.


• Collaborate with RTL designers and architects to identify and resolve functional issues.


• Contribute to verification methodology, reusable components, and automation.

Mandatory Skills

• Strong experience in SystemVerilog and UVM.


• Good understanding of ASIC/SoC/IP Design Verification methodologies.


• Hands-on experience with PCIe protocol verification is highly preferred.


• Knowledge of PCIe LTSSM, TLP, DLLP, link training, configuration and error handling is an advantage.


• Experience with VCS / Xcelium / Questa or similar simulators.


• Good understanding of functional coverage, assertions, constrained-random verification and regression.


• Strong RTL debugging and waveform analysis skills.

Good to Have

• Experience with Ethernet, CXL, DDR, USB, MIPI or AMBA/AXI protocols.


• Python/Perl/Tcl/Shell scripting.


• Experience in subsystem/SoC-level verification.


• Formal verification or CDC knowledge.

Education

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI or related discipline.

Preferred Candidate

Candidates with strong PCIe protocol + SystemVerilog + UVM experience and hands-on ASIC/SoC verification exposure are preferred.