Design Verification (DV) Engineer

Nxtwavesemi; India; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Nxtwavesemi in India is seeking a motivated Design Verification (DV) Engineer to contribute to verification across IP, subsystem, and SoC levels, developing reusable environments and integrating VIPs. You will create testbenches, sequences, drivers, monitors, and scoreboards, debug failures, and collaborate with RTL, firmware, and silicon-validation teams to achieve verification closure.

A strong foundation in Verilog/SystemVerilog and UVM, plus experience with constrained-random testing and

Qualifications

• Strong fundamentals in Verilog/SystemVerilog and digital logic.
• Understanding of UVM, OOP, TLM, and reusable verification components.
• Experience with simulation, constrained-random verification and functional coverage.

Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level verification.
• Translate design specs into verification plans, test scenarios, and coverage goals.
• Create testbenches, sequences, drivers, monitors, scoreboards, reference models, assertions, and functional coverage.
• Integrate protocol and memory VIPs for block, subsystem, and SoC verification.
• Create and execute directed, constrained-random, protocol, error, performance, and regression tests.
• Perform functional, integration, and system-level verification and debug.
• Analyze simulation/regression failures and conduct root-cause analysis.
• Track functional and code coverage and identify verification gaps.
• Support CSR/RAL verification, firmware-driven testing, and system-level scenarios.
• Collaborate with RTL, architecture, firmware, emulation, and silicon-validation teams for verification sign-off.

Skills

SystemVerilog

UVM

Verification

Debugging

Regression testing

Python scripting

Education

B.E./B.Tech in Electronics & Communication Engineering

M.E./M.Tech in Electronics & Communication Engineering

Tools

VIP development

Emulation

FPGA-based verification

Job description

We are looking for a motivated Design Verification (DV) Engineer to join our semiconductor engineering team. The candidate will contribute to verification activities across IP, subsystem, and SoC levels, ensuring that designs meet functional, protocol, performance, and specification requirements.The role involves developing reusable verification environments, integrating verification IP (VIP), creating test scenarios, debugging simulation and regression failures, and contributing to verification closure using industry standard methodologies and tools.

What You'll Do

• Develop and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level verification.
• Understand design specifications and translate them into verification plans, test scenarios, and coverage goals.
• Develop testbenches, sequences, drivers, monitors, scoreboards, reference models, assertions, and functional coverage.
• Integrate and configure protocol and memory VIPs for block, subsystem, and SoC-level verification.
• Create and execute directed, constrained-random, protocol, error, performance, and regression tests.
• Perform functional, integration, and system-level verification and debug.
• Analyze simulation and regression failures and perform root-cause analysis.
• Track functional and code coverage and identify verification gaps.
• Support CSR/RAL verification, firmware-driven testing, and system-level scenarios where applicable.
• Collaborate with RTL, architecture, firmware, emulation, and silicon-validation teams through verification sign off.

Required Skills

• Good understanding of Digital Logic and Digital System Design.
• Strong fundamentals in Verilog/SystemVerilog.
• Understanding of UVM methodology, OOP, TLM, configuration, and reusable verification components.
• Understanding of simulation, constrained-random verification, functional coverage, and SVA.
• Good understanding of verification planning, debugging, and regression methodologies.
• Basic understanding of communication protocols and interface behavior.

Good to Have

• VIP development, integration, configuration, and protocol compliance verification.
• PCIe, DDR, HBM, Ethernet, CXL, AMBA, USB, MIPI, SPI, or I2C verification.
• CSR/RAL, performance verification, power-aware verification, CDC/RDC, formal verification, emulation, or FPGA-based verification.
• Python, Perl, TCL, shell, or verification automation.

Educational Qualification

B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering, Electrical Engineering, Computer Engineering, VLSI, Microelectronics, or a related field.

What We Look For

• Strong technical fundamentals and a practical engineering mindset.
• Ability to understand specifications and solve complex technical problems.
• Effective debugging, analysis, and communication skills.
• Ability to work independently and collaboratively across engineering teams.
• Curiosity and willingness to learn new semiconductor technologies and methodologies.

What You Will Work On

• VIP Integration
• DDR
• HBM
• Ethernet
• CXL
• AMBA
• USB
• MIPI
• SPI
• I2C
• UVM
• SVA
• RAL/CSR
• Functional Coverage
• Regression
• Simulation & Debug

Closing Statement

Verify complex semiconductor designs from individual IP functionality through integrated subsystem and SoC behavior.