Design Engineer II

Cadence Design Systems; Bengaluru; Sur place; INR 4 000 000 - 6 500 000; Plein temps

Résumé du poste

Cadence Design Systems in Bengaluru seeks a technical leader to charter and validate analog and digital IP based silicon solutions. You will guide day‑to‑day lab tests and silicon characterization, and collaborate with remote teams worldwide to deliver results on schedule.

The role demands ownership of tasks, strong communication, and the ability to mentor a small team of engineers. Proficiency with Ethernet, PCIe, UCIe protocols, Lab equipment, and Verilog RTL (FPGA) with Python/C/C++ is

Qualifications

• Experience in post-silicon PHY testing and interoperability
• Ability to manage a small team and coordinate with remote groups
• Strong lab equipment troubleshooting and data analysis

Responsabilités

• Lead/mentor engineers in lab tests and silicon characterization
• Own test suite development and calibration labs
• Coordinate with R&D and Marketing to define scope
• Ensure timely delivery of results and compliance with standards

Connaissances

Leadership

Lab testing

Silicon characterization

Verilog RTL

Python

C/C++

Formation

BTech/MTech in a relevant field

Outils

Oscilloscopes

Bit Error Rate Testers

Protocol Exercisers

Description du poste

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The role will be a key player in organization responsible for Characterizing and validating Analog and Digital IP based Silicon Solutions at Cadence.

Candidate should possess strong leadership skills with ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterization activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills, are must have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.

Minimum Qualifications & Professional Experience:

• 2-10years (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 5-7 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.

• Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.
• Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.
• Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.
• Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.
• Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.
• Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification
• Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

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