Design Verification Engineer

Cadence; Dadri; On-site; INR 1,200,000 - 2,400,000; Full time

Benefits offered by this job

Learning and development programs

Collaborative culture

Cutting-edge technology projects

Job summary

Cadence is a pivotal leader in electronic design with 30+ years of software expertise. We seek a highly motivated verification engineer focused on VIP development, interacting with customers and cross-functional teams to deliver robust verification IP.

The role requires strong communication, quick adaptation to new protocols, and hands-on experience in SV/UVM, C/C++, and digital electronics, within a diverse team driving innovative solutions for dynamic markets.

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics field is required.
• 4–6 years of domain experience in functional verification.
• Proficiency in SV/UVM with strong debugging skills and C/C++ scripting.

Responsibilities

• Responsible for design, development, verification and deployment of the VIP.

Skills

SV/UVM

C/C++

Scripting

VIP development

Digital electronics

Communication

Cross-functional collaboration

Education

BE/BTech/ME/MS/MTech in Electrical/Electronics

Job description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other - every day.

About the Role

We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers.

Responsibilities

• Responsible for the design, development, verification and deployment of the VIP.

Qualifications

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Required Skills

• 4 to 6 years of domain experience
• Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills.
• Hands-on knowledge of C/C++/Scripting.
• Working experience on layered Protocols - UCIe, PCIe, CXL, Ethernet, Ualink.
• Prior VIP usage and development experience is a plus.
• Strong Digital Electronics and Programming fundamentals.
• Self-motivated individuals with strong analytical and communication skills.

Preferred Skills

• Demonstrate adaptability in a fast-paced environment, showing resilience in the face of challenges and maintaining a positive attitude.
• Exhibit a strong commitment to continuous learning and professional development, staying abreast of industry trends and technologies.
• Foster a collaborative team environment by being approachable and supportive.
• Display a proactive approach to problem-solving, taking initiative, and anticipating potential issues before they arise.