Design Engineering Manager

Cadence; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Benefits offered by this job

Opportunities for learning and development

Employee-friendly policies

Collaborative culture

Job summary

Cadence is looking for a Design Engineering Manager in Bangalore. This role involves leading the Physical Layer Electrical Validation infrastructure development and validating Cadence's High Speed SERDES Test chips. Candidates should have extensive experience in Post-Silicon Physical Layer Electrical Validation, familiarity with various High speed SERDES protocols, and hands-on skills with lab equipment. A collaborative culture encourages innovation while providing ample learning opportunities through employee-friendly policies.

Qualifications

• 6­–10 years (with BTech) or 4­–8 years (with MTech) of experience in Post­-Silicon Physical Layer Electrical Validation.
• Deep Physical Layer electrical validation experience on one High speed SERDES protocol like PCIe, USB.
• Strong hands-on experience in using lab equipment such as Oscilloscopes and Network Analyzers.

Responsibilities

• Lead pre silicon Physical Layer Electrical Validation infrastructure development.
• Define test plans for testing the compliance of Test chips.
• Generate high quality test reports based on test results.

Skills

Post-Silicon Physical Layer Electrical Validation

High speed SERDES protocol

Lab equipment usage

FPGA Design

Team management

Education

BTech or MTech

Tools

Oscilloscopes

Network Analyzer

Bit Error Rate Tester (BERT)

Labview

Python

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Design Engineering Manager

Location: Bangalore

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

Cadence Advantage

• The opportunity to work on cutting‑edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee‑friendly policies focus on the physical and mental well‑being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary

We have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of "Design Engineering Manager".

The responsibility entails leading pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation efforts primarily on Cadence's High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.

Minimum Qualifications

• 6‑10 years (with BTech) or 4‑8 years (with MTech) of experience in Post‑Silicon Physical Layer Electrical Validation
• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO etc
• Strong hands‑on experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc

Preferred Qualifications

• Experience managing small teams (at least 2 members and above)
• Experience leading the complete post silicon validation efforts for at least one full project
• 1‑2 years of experience in FPGA Design, PCB schematic and layout design & prototyping
• Pre‑Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring‑up & Debug.
• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL
• Experience conducting hiring interviews and mentoring new hires
• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.

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