Layout Engineer

118-WW TMG MFG OPS; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

118-WW TMG MFG OPS seeks an experienced layout engineer to lead the full-chip layout lifecycle from definition to production. You will work with designers to capture IC architecture, balance area and performance, and ensure design-rule compliance.

You will collaborate with process, design, and packaging teams, debug antennas, and mentor junior engineers, delivering high-quality layouts on schedule.

Qualifications

• Experience in full chip layout from definition through release to production.
• Expertise in LVS, DRC, ERC, and antenna debugging.
• Strong knowledge of analog/mixed-signal layout verification and device matching.
• Familiarity with multiple process nodes (40nm–180nm) and BiCMOS/BCD.
• Proficiency with layout optimization to balance area, performance and timing.

Responsibilities

• Frame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project
• Work closely with designers to understand the architecture and key requirements for the IC
• Strike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams
• Work closely with Process development team to carry out PDK, P-cell and Design rule updates
• Work closely with Packaging engineer to develop custom lead-frames for various packages
• Analysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic
• Routinely develop test vehicles for new process & package technology development
• Mentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms
• Responsible for the final layout which meets the design expectations and layout checklist.
• Identify improvements needed in process/ quality/ cycle time and take up necessary initiatives

Skills

Full chip layout

LVS, DRC, ERC

Analog/mixed-signal layout

Device matching

Device physics knowledge

Technology nodes 40/65/90/130/180nm

Layout tools: Virtuoso, Assura, PVS, V

Automation/SKILL coding

Teamwork & communication

Initiative & drive

Tools

Virtuoso XL

Assura

PVS

Voltas

Job description

Roles and responsibilities:

• Frame the layout schedule, effort estimation, risk and mitigation plan of layout activities for all layout engineers in the project
• Work closely with designers to understand the architecture and key requirements for the IC
• Strike right balance of area, performance and schedule during layout development by collaborating with design, packaging and process teams
• Work closely with Process development team to carry out PDK, P-cell and Design rule updates
• Work closely with Packaging engineer to develop custom lead-frames for various packages
• Analysis and closure of Electro Migration, Thermal gradients, ESD/LU performance and layout parasitic
• Routinely develop test vehicles for new process & package technology development
• Mentor and guide junior layout engineers/contract engineers, review their work and provide feedback to meet the quality and schedule norms
• Responsible for the final layout which meets the design expectations and layout checklist.
• Identify improvements needed in process/ quality/ cycle time and take up necessary initiatives

Knowledge and skills:

• Full chip layout experience from definition through release of IC to production
• Strong LVS, DRC, ERC, and antenna debug skills
• Proficient in analog and mixed-signal layout techniques and verification process including Device Matching, Power Bus design, avoiding Cross-talk, ESD/LU protection techniques
• Good understanding about all layout parasitics (R, C, diodes, BJTs)
• Good understanding of device physics and semiconductor fabrication process
• Must have worked on some of the Technologies like: 40nm, 65nm, 90nm, 130nm, 180nm, BiCMOS, BCD
• Should be well versed with tools such as Virtuoso XL/Assura /PVS/Voltas
• Ability to quickly ramp up on new tools/ process and mentor LEs
• Experience in automation/ SKILL coding for reducing cycle time/ quality checks will be an added advantage
• Requires excellent teamwork, good communication, strong problem-solving and documentation skills.
• Strong time management skills for on-time project delivery
• Ability to take initiatives and drive for results