Junior ASIC Engineer

Acesoft Labs; Hyderabad; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Acesoft Labs in Hyderabad is seeking an ASIC Engineer (entry to mid-level) to join our design team. You will work across verification, RTL design and physical design activities, using Verilog and SystemVerilog and contributing to UVM test environments.

You will run RTL synthesis, implement timing constraints, and participate in RTL2GDS flows with Cadence and Mentor tools. Collaboration with cross-functional teams to meet project milestones is essential, and you will develop test benches and

Qualifications

• Proficient in Verilog, SystemVerilog, and UVM.
• Experience in RTL design and SOCC verification.
• Familiarity with ASIC design flows and physical design concepts.
• Willingness to work with Cadence/Mentor tools.

Responsibilities

• Develop and verify ASIC designs using Verilog, SystemVerilog, and UVM methodologies.
• Perform RTL design and SOCC verification.
• Execute RTL synthesis to optimize performance, power, and area.
• Develop and implement timing constraints for functional and test modes.
• Participate in physical design activities, including RTL2GDS implementation (Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification).
• Debug complex designs and high-speed interfaces (DDR, PCIe, ONFI).
• Utilize lab equipment like Logic Analyzers and Oscilloscopes for debugging.
• Develop and maintain test benches and verification environments.
• Write and debug scripts in Tcl/Tk/Perl.
• Work with Cadence tools (Innovus, Genus, Tempus) and Mentor Caliber.
• Collaborate with cross-functional teams to achieve project milestones.
• Contribute to the development and improvement of ASIC design and verification methodologies.

Skills

Verilog

SystemVerilog

UVM

RTL design

SOCC verification

Synthesis

Timing constraints

Cadence tools

Mentor tools

Scripting Tcl/Perl

Debugging

Communication

Teamwork

Tools

Innovus

Genus

Tempus

Caliber

Job description

Job Title: ASIC Engineer (Entry to Mid-Level)

Job Description

We are seeking motivated ASIC Engineers to join our dynamic team. This role encompasses a range of responsibilities from foundational verification to physical design and synthesis. The ideal candidate will have a solid understanding of Verilog and SystemVerilog, with a keen interest in expanding their knowledge in ASIC design and verification.

Responsibilities

• Develop and verify ASIC designs using Verilog, SystemVerilog, and UVM methodologies.
• Perform RTL design and SOCC verification.
• Execute RTL synthesis to optimize performance, power, and area.
• Develop and implement timing constraints for functional and test modes.
• Participate in physical design activities, including RTL2GDS implementation (Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification).
• Debug complex designs and high-speed interfaces (DDR, PCIe, ONFI).
• Utilize lab equipment like Logic Analyzers and Oscilloscopes for debugging.
• Develop and maintain test benches and verification environments.
• Write and debug scripts in Tcl/Tk/Perl.
• Work with Cadence tools (Innovus, Genus, Tempus) and Mentor Caliber.
• Collaborate with cross-functional teams to achieve project milestones.
• Contribute to the development and improvement of ASIC design and verification methodologies.

Required Skills

• Proficiency in Verilog, SystemVerilog, and UVM.
• Strong debugging skills.
• Experience in RTL design and SOCC verification.
• Knowledge of ASIC design and verification flows.
• Understanding of physical design concepts (RTL2GDS).
• Experience with synthesis and STA.
• Ability to work with Cadence and Mentor tools.
• Good communication and teamwork skills.
• Scripting experience (Tcl/Tk/Perl) is a plus.

Experience

0-7 years of relevant experience.