ASIC Engineer

NVIDIA; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

NVIDIA's Global Flows Team seeks an ASIC Engineer in Bengaluru to advance RTL design-quality methodologies, including CDC, RDC, lint, and power insertion. You will analyze flow results, set readiness criteria, and collaborate across RTL build, DFT, clocks, reset, low-power, and CAD teams to drive silicon readiness.

You should have 3+ years in ASIC/SoC RTL design, strong Verilog/SystemVerilog skills, and experience with Linux scripting.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 3+ years of proven experience in ASIC or SoC RTL design or design-methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Knowledge of digital design and microarchitecture, including pipelines, FSMs, clock/reset architectures, synchronizers, handshakes, async FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low-power verification, synthesis, or timing constraints.
• Ability to relate methodology results to RTL behavior and perform detailed root-cause analysis.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

Responsibilities

• Analyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.
• Establishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.
• Collaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
• Assessing new tool releases and methodology capabilities, coordinating their integration into project environments.
• Improving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.

Skills

Verilog/SystemVerilog

RTL design

Scripting (Python/Tcl/Perl)

Debugging

Collaboration

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Tools

Meridian

SpyGlass

VC CDC

Questa CDC

Design Auditor

Power insertion

Job description

NVIDIA builds accelerated computing platforms that are redefining AI, data centers, autonomous systems, and scientific computing. The Global Flows Team advances RTL quality and sign-off methodologies used across NVIDIA CPU programs. This position connects digital implementation and microarchitecture with CDC, RDC, RTL-NA/DA, PSI and lint. The work spans methodology development, technical analysis, tool deployment, and coordination across development and CAD organizations. Results improve RTL quality, project predictability, and readiness for silicon.

What you'll be doing

As an ASIC Engineer, you will embark on an ambitious journey to develop and deploy innovative RTL design-quality methodologies. These include CDC, RDC, Netlist/Design Auditors, Power Insertion, lint, and related structural checks. Your role will involve:

• Analyzing flow results in the context of design intent and identifying root causes across RTL, constraints, tools, and methodology.
• Establishing quality requirements and readiness criteria for project achievements while monitoring regressions, violation trends, and sign-off status.
• Collaborating across RTL build, DFT, clocks, reset, low-power, physical-design, verification, and CAD teams to resolve technical issues.
• Assessing new tool releases and methodology capabilities, coordinating their integration into project environments.
• Improving runtime, debug efficiency, waiver management, reporting, and training through automation, reusable scripts, and engineering guidelines.

What we need to see

We are seeking a professional with:

• A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• 3+ years of proven experience in ASIC or SoC RTL design or design-methodology.
• Practical experience with Verilog or SystemVerilog build, analysis, and debugging.
• Knowledge of digital design and microarchitecture, including pipelines, finite-state machines, clock/reset architectures, synchronizers, handshakes, asynchronous FIFOs, metastability, and power-domain crossings.
• Experience with front-end methodologies such as lint, CDC/RDC, structural RTL analysis, low‑power verification, synthesis, or timing constraints.
• The ability to relate methodology results to RTL behavior and perform detailed root‑cause analysis.
• Experience with Linux development environments and scripting in Python, Tcl, Perl, shell, or a comparable language.

Ways to stand out from the crowd

To shine in this role, you may possess:

• Experience with RTL integration, design bring‑up, or multi‑team debugging at the unit, subsystem, chiplet, or SoC level.
• Familiarity with tools such as Meridian, SpyGlass, VC CDC, Questa CDC, Design Auditor, Power insertion, or equivalent.
• Knowledge of UPF and low‑power RTL implementation or verification.
• Experience with SDC, synthesis, static timing analysis, formal verification, or equivalence checking.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.