Job Posting Title Principal ASIC Design Engineer

MaxLinear, Inc.; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

MaxLinear, Inc. is seeking a Principal ASIC Design Engineer to join our Digital ASIC Design group in Bengaluru, India. This senior role involves leading the architecture and RTL design of complex packet processing systems, integrating components in multi-CPU SoCs for optimal power efficiency.

The ideal candidate has over 15 years of experience in ASIC design, a strong background in digital logic, and proficiency with industry-standard design tools. You will contribute to innovative design solutions while collaborating across teams.

Qualifications

• 15+ years of experience in Digital ASIC implementation including RTL design skills.
• Proven expertise in translating engineering requirements to ASIC solutions.
• Strong analytical and problem-solving skills.

Responsibilities

• Lead architecture, micro-architecture, and RTL design of packet processing systems.
• Integrate logic components in multi-CPU SoC environments.
• Apply design and verification methodologies effectively.

Skills

Digital ASIC design

Verilog/System Verilog/VHDL

Packet processing architectures

Digital logic design

Education

BE/M.Tech in Electronics Engineering

Tools

STA tools

UVM

Python

Job description

Responsibilities

MaxLinear is seeking a Principal ASIC Design Engineer to join our Digital ASIC Design group. The Digital ASIC team delivers innovative and scalable ASIC solutions addressing complex challenges in the optical and wireless communications domain.

In this senior technical role, you will lead the architecture, micro-architecture, and RTL design of high-performance packet processing, interface, and system control blocks. You will also be responsible for the integration of these logic components along with custom or 3rd party embedded processors in multi‑CPU SoC environments, contributing to highly integrated and power‑efficient designs.

This position requires expertise in packet processing architectures, understanding of computer networking fundamentals, strong grounding in digital design and CMOS logic, and experience applying industry‑standard design and verification methodologies. Proficiency with modern design and verification tools is essential. Experience with low‑power design techniques is highly desirable.

The ideal candidate is a curious, highly motivated engineer with a relentless drive to learn, innovate, and solve complex problems. You bring a “never give up” attitude and thrive when tackling technically demanding challenges. You value collaboration across disciplines and leverage the differences in skill sets with cross‑domain teams to contribute to collective problem‑solving. You aspire to make a lasting technical impact while continuously raising the bar for design quality and engineering excellence.

Qualifications

• BE/M.Tech in Electronics Engineering
• 15+ years of experience in Digital ASIC implementation at subsystem level or chip level including RTL design skills using Verilog, System Verilog or VHDL
• Strong analytical and problem‑solving skills
• Proved expertise in translating engineering requirements to working ASIC solutions meeting PPA
• Strong fundamentals and proven expertise in digital logic design, CMOS technology and ASIC design methodology
• Strong fundamentals in basic circuit design, device physics
• Strong fundamentals in programming, CPU architecture and SOC systems
• Specialization in Communication systems, Networking, or Processor systems
• Passion for learning and engineering great solutions
• Block level verification using SV, UVM, Python or C using industry standard tools
• Basic knowledge and ability to synthesize and perform STA with industry standard tools either for ASIC or FPGA
• Proven written and verbal communication skills that demonstrate clarity of thought and conviction
• Working knowledge of one or more scripting languages and ability to use them to automate/accelerate design and analysis tasks