ASIC Design Engineer

HPE Aruba Networking; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading tech company in India is seeking an experienced ASIC Design Engineer to drive the development of next-generation ASICs for networking systems. The role demands over 5 years of ASIC design experience. Candidates should possess solid knowledge of tools like Synopsys Design Compiler and should be adept at collaborating across teams. The company promotes a culture of communication, empowerment, and innovation, offering significant opportunities for personal growth and financial rewards.

Qualifications

• 5+ years of ASIC design experience.
• Knowledge of networking protocols like Ethernet and FCoE.
• Strong problem-solving and ASIC debugging skills.

Responsibilities

• Define and architect high-performance blocks for networking ASICs.
• Perform micro-architecture and logic design for optimal throughput.
• Collaborate in developing test plans and debugging failures.

Skills

ASIC design experience

Communication skills

Problem solving

ASIC debugging

Tools

Synopsys Design Compiler

Verplex LEC

Spyglass

Job description

Silicon Systems Technology team seeks ASIC Design Engineers to develop next generation of ASICs for new core routers, switches, and firewalls.

Experience: 5+ years

Opportunity Snapshot

• We are looking to hire sharp ASIC Design Engineer with excellent communication and leadership skills.
• You will be part of a fast paced team responsible for delivering high-speed ASICs for large, complex systems. You will have a significant opportunity to interact with system design teams across geographies.
• Open communications, empowerment, innovation, teamwork and customer success are the foundations of the team with "pay for performance" culture. Thus, you set your own limits for learning, achievements and rewards.

Responsibilities

• Define and architect high-performance blocks for the latest, most advanced networking ASICs
• Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
• Collaborate with the verification team in the development of the testplan and assist in debugging test failures
• Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

Required Skills

• 5+ years of ASIC design experience
• Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
• Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
• Knowledge of high performance memory subsystems
• Knowledge of multi-domain clock synchronization and high-speed serial interfaces
• Strong problem solving and ASIC debugging skills
• Excellent written and verbal communications skills