ASIC Design Mid Level Professional

Tessolve; Coimbatore District, Bengaluru, Hyderabad; On-site; INR 600,000 - 1,200,000; Full time

Job summary

Tessolve is seeking a skilled engineer to design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL. The ideal candidate will translate architectural specifications into synthesizable RTL code and perform RTL simulations while collaborating with verification engineers.

You will support synthesis, timing analysis, and optimize designs for performance and power in a collaborative team environment. A degree in Electrical or Computer Engineering is required.

Qualifications

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design principles.
• Proficient in RTL design using Verilog/System Verilog or VHDL.
• Familiarity with ASIC or FPGA design flows.
• Experience with simulation tools and debugging techniques.
• Basic understanding of synthesis, static timing analysis, and formal verification.
• Strong problem solving and communication skills.
• Ability to work collaboratively in a team environment.

Responsibilities

• Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL.
• Translate architectural specifications into synthesizable RTL code.
• Perform RTL simulations and debug logic issues.
• Collaborate with verification engineers to develop and review test plans and coverage.
• Support synthesis, timing analysis, and logic equivalence checks.
• Interface with physical design and DFT teams to ensure design feasibility and testability.
• Optimize designs for performance, area, and power.
• Participate in design and code reviews.

Skills

RTL design using Verilog/System Verilog

Digital logic design principles

ASIC or FPGA design flows

Simulation tools (e.g., ModelSim, VCS)

Debugging techniques

Synthesis

Static timing analysis (STA)

Problem solving

Communication skills

Team collaboration

Education

Bachelors or Masters degree in Electrical Engineering

Job description

Responsibilities

• Design and implement digital circuits at the RTL level using Verilog/SystemVerilog or VHDL.
• Translate architectural specifications into synthesizable RTL code.
• Perform RTL simulations and debug logic issues.
• Collaborate with verification engineers to develop and review test plans and coverage.
• Support synthesis, timing analysis, and logic equivalence checks (LEC).
• Interface with physical design and DFT teams to ensure design feasibility and testability.
• Optimize designs for performance, area, and power.
• Participate in design and code reviews.

Required Skills and Qualifications

• Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design principles.
• Proficient in RTL design using Verilog/System Verilog or VHDL.
• Familiarity with ASIC or FPGA design flows.
• Experience with simulation tools (e.g., ModelSim, VCS) and debugging techniques.
• Basic understanding of synthesis, static timing analysis (STA), and formal verification.
• Strong problem solving and communication skills.
• Ability to work collaboratively in a team environment.