GLS Verification Engineer

LeadSoc Technologies Pvt Ltd; Bengaluru; On-site; INR 1,900,000 - 2,700,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd is seeking an experienced GLS Verification Engineer with strong gate-level simulation, timing validation, and SoC verification. The role requires hands-on debugging of timing, CDC/RDC, low-power, and DFT issues across RTL-to-gate flows.

You will execute GLS with and without SDF, perform SDF timing validation, analyze STA/CDC/RDC violations, and validate power intent (UPF) and DFT flows.

Qualifications

• 8–12 years of hands-on ASIC/SoC verification or GLS experience.
• Strong hands-on with GLS, SDF annotation, and timing simulation.
• Deep understanding of STA, CDC, RDC concepts and debugging.
• Experience with low-power verification and UPF.
• Proficiency in Verilog/SystemVerilog and simulation methodologies.
• Experience with industry-standard simulators and STA/CDC tools.

Responsibilities

• Execute Gate-Level Simulation (GLS) with and without SDF annotation.
• Perform SDF timing validation and debug setup/hold, timing, and simulation failures.
• Analyze and debug STA, CDC, and RDC violations with design and implementation teams.
• Validate low-power design flows, including power intent and UPF-related scenarios.
• Perform DFT validation, including scan, MBIST, ATPG, and test-mode simulations.
• Correlate RTL vs. gate-level behavior and identify functional/timing mismatches.
• Debug X-propagation, reset, clock, timing, and initialization issues in GLS.
• Develop and maintain simulation/debug scripts using Shell, Python, or Tcl.
• Work closely with RTL, PD, STA, DFT, and SoC teams to drive issues to closure.

Skills

ASIC/SoC Verification

GLS

timing simulation

SDF annotation

STA

CDC

RDC

low-power verification

UPF

DFT concepts

Verilog/SystemVerilog

simulation/debug methodologies

Job description

We are looking for an experienced GLS Verification Engineer with strong expertise in gate-level simulation, timing validation, and SoC verification. The role requires hands-on experience debugging complex timing, CDC/RDC, low-power, and DFT-related issues across RTL-to-gate flows.

Key Responsibilities

• Execute Gate-Level Simulation (GLS) with and without SDF annotation.
• Perform SDF timing validation and debug setup/hold, timing, and simulation failures.
• Analyze and debug STA, CDC, and RDC violations in collaboration with design and implementation teams.
• Validate low-power design flows, including power intent and UPF-related scenarios.
• Perform DFT validation, including scan, MBIST, ATPG, and test-mode simulations.
• Correlate RTL vs. gate-level behavior and identify functional/timing mismatches.
• Debug X-propagation, reset, clock, timing, and initialization issues in GLS.
• Develop and maintain simulation/debug scripts using Shell, Python, or Tcl.
• Work closely with RTL, PD, STA, DFT, and SoC teams to drive issues to closure.

Required Skills

• 8-12 years of experience in ASIC/SoC Design Verification or GLS.
• Strong hands-on experience with GLS, SDF annotation, and timing simulation.
• Solid understanding of STA, CDC, and RDC concepts and debug.
• Experience with low-power verification and UPF.
• Strong understanding of DFT concepts and validation flows.
• Proficiency in Verilog/SystemVerilog and simulation/debug methodologies.
• Experience with industry-standard simulators and STA/CDC tools.
• Strong debugging, problem-solving, and cross-functional collaboration skills.

Good to Have

• Experience with advanced SoC/full-chip verification and complex clock/reset architectures.
• Scripting expertise in Python, Tcl, or Shell.
• Exposure to advanced process nodes and large-scale SoC tapeout/validation environments.