GLS Verification Engineer

HCLTech; Hyderabad, Chennai District, Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

HCLTech is seeking a GLS Verification Engineer to verify and validate GLS flows for complex designs, collaborating with cross-functional teams to ensure functional accuracy and reliability.

The role emphasizes development of test benches, regression testing, and staying updated with GLS verification best practices to drive process improvements.

Qualifications

• Bachelor's or Master's in Electronics/CE/EE.
• Experience in GLS verification in semiconductor/tech industry.
• Strong HDL (Verilog/SystemVerilog/VHDL) skills.

Responsibilities

• Develop and execute GLS verification plans with full coverage.
• Create and optimize GLS test benches and verification environments.
• Analyze and debug gate-level functional and timing issues with design teams.
• Perform regression testing and track issues to closure.
• Review RTL, synthesis reports, and design specs to align verification with intent.
• Support sign-off with verification reports and metrics for stakeholders.

Skills

GLS verification

HDL languages

Analytical/problem-solving

Teamwork/communication

Education

Bachelor's/Master's in Electronics/CE/EE

Tools

Synopsys VCS

Cadence Xcelium/Incisive

Mentor Questa

Job description

Overview of the Role

The GLS Verification Engineer will play a pivotal role in verifying and validating GLS (Gate Level Simulation) flows for complex semiconductor or system designs. This position is crucial in ensuring the functional accuracy, performance, and reliability of advanced technology solutions delivered to HCLTechs global clientele. The role involves close collaboration with cross-functional engineering teams to deliver high-quality products that uphold HCLTechs standards of excellence and innovation.

Detailed Responsibilities

• Develop and execute comprehensive GLS verification plans, ensuring full coverage for assigned modules or projects.
• Create, maintain, and optimize GLS test benches, simulation environments, and verification infrastructure.
• Analyze and debug functional and timing issues at the gate level, collaborating with design and implementation teams to resolve discrepancies.
• Perform regression testing, document results, and track issues to closure.
• Review and interpret design specifications, RTL code, and synthesis reports to align verification efforts with design intent.
• Participate in design and verification reviews, contributing technical insights and recommendations.
• Support sign-off activities by generating verification reports and metrics for project stakeholders.
• Stay updated on industry best practices, tools, and methodologies in GLS verification and contribute to process improvements.

Skill Requirements

• Bachelors or Masters degree in Electronics Engineering, Computer Engineering, Electrical Engineering, or a related discipline.
• Proven experience in GLS (Gate Level Simulation) verification within the semiconductor or technology industry.
• Strong proficiency in HDL languages (Verilog, SystemVerilog, or VHDL).
• Hands-on expertise with industry-standard EDA tools for simulation, waveform analysis, and debugging (e.g., Synopsys VCS, Cadence Incisive/Xcelium, Mentor Questa).
• Solid understanding of digital design, synthesis, static timing analysis, and related concepts.
• Excellent analytical, problem-solving, and troubleshooting skills.
• Effective communication and teamwork abilities.