Lead/Manager / Director GLS Verification Engineer

SiSoC Semiconductor Technologies Pvt Ltd.

Bengaluru Urban

Remote

INR 1,500,000 - 2,500,000

Full time

14 days+

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Job summary

A leading IP and Design services company is seeking a Lead Design Verification Engineer with over 8 years of experience. In this full-time remote role, you will manage design verification tasks for ASIC/SoC designs, develop strategies, and collaborate with cross-functional teams. Ideal candidates should possess strong skills in SystemVerilog and have experience with large ASIC designs. This position offers an exciting opportunity to work in a dynamic team and contribute to cutting-edge projects.

Qualifications

8+ years of experience in ASIC design verification.
Proficient in verification methodologies and testbench development.
Strong debugging skills in SystemVerilog or VHDL.

Responsibilities

Lead design verification tasks for ASIC/SoC designs.
Develop and implement verification strategies.
Collaborate with cross-functional teams.

Skills

Experience of GLS of large ASIC designs

Solid RTL and netlist debugging skills

C-programming experience

Understanding of long simulation time reduction

Verdi experience on large designs

Tools

git

Gerrit

Jenkins

Job description

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SiSoC Semiconductor Technologies Pvt. Ltd. is a leading IP and Design services company specializing in Digital, Analog, and Mixed Signal design and verification. With expertise spanning ASIC/SoC Design Verification, Physical Design, DFT, FPGA Emulation, Embedded Software, and IoT solutions, we deliver high-quality and reliable engineering services. Our skilled team leverages advanced tools, technologies, and methodologies to provide end-to-end design and verification, including specification definition, RTL coding, synthesis, and verification environment development. At SiSoC, our specialty is integrating modern design practices with cutting‑edge innovation to meet the unique needs of each project.

Role Description

This is a full-time remote role for a Lead/Manager/Director Design Verification Engineer. The selected candidate will lead and manage design verification tasks, including verifying ASIC/SoC designs, developing and executing verification strategies, and creating and maintaining test benches. Day-to-day responsibilities include collaborating with cross-functional teams, defining and implementing advanced verification methodologies, performing debugging, and ensuring adherence to quality standards and timelines.

Exp: 8+ Years

What you will do

We are looking for someone to strengthen the ASIC Top level team with respect to GLS. We are currently developing two main dies to be instantiated in various configurations in different ASICs. One die consists of a huge number of DSPs and even more accelerator IPs for different type of computing. The same die also a common memory used by all DSPs and accelerators IPs.

Role in the Team

When working with GLS you will be involved in

Tailor the SystemVerilog/UVM testbench to support GLS
Verify power-up and reset sequence
Verify all interfaces that are used for the silicon bring-up

Skills you must possess

Experience of GLS of large ASIC designs, zero delay as well as with annotated SDF.
Solid RTL and netlist debugging skills in SystemVerilog or VHDL designs.
C-programming experience, to be able to modify tests if necessary
Understanding of how to reduce long simulation time of very large ASIC designs. This e.g. requires an understanding of how to user grey box/black box concept from IP level to chiplet level.
Understand what to initialize and when, to get the GLS working.
Experienced with Verdi on large designs.

Other desired knowledge and experience