Formal Verification Engineer

ACL Digital; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

ACL Digital in Bengaluru seeks an experienced Senior Formal Verification Engineer to drive end-to-end formal verification of complex IP/sub-system SoC designs. The engineer should operate independently, contribute deep technical expertise, and deliver high-quality sign-off packages in a fast-paced environment.

Responsibilities include developing formal verification plans, writing SVA/PSL properties, debugging counterexamples, and delivering complete sign-off packages on schedule.

Qualifications

• 4–20 years of hands-on FPV experience.
• Proficiency in SystemVerilog Assertions (SVA) and formal tools.
• Strong RTL design understanding incl. FSMs, clock/power domains.
• Knowledge of AMBA AXI/APB/AHB interfaces.
• Experience with abstraction, COI analysis, vacuity checks, formal completeness metrics.
• Excellent debugging and analytical problem-solving skills.
• Experience with multilayer buses/interconnects (preferred).
• Knowledge of scripting languages (Python, Perl, TCL).

Responsibilities

• Develop and execute formal verification plans for IP-level and subsystem designs.
• Write high-quality SVA/PSL properties and build complete formal environments.
• Perform property proofs, coverage closure, abstraction modeling, and constraint analysis.
• Debug counterexamples and root-cause design issues.
• Provide regular reports, documentation, and formal sign-off deliveries.
• Collaborate with Verification lead, RTL designers, and simulation teams to ensure design correctness.

Skills

FPV

SystemVerilog Assertions

Jasper Gold

RTL Design

Abstraction

Debugging

Scripting (Python)

Perl

TCL

Tools

Jasper Gold

Job description

Job Description: Senior Formal Verification Engineer

Seeking an experienced Senior Formal Verification Engineer to drive endtoend formal verification of complex IP/Sub-system SoC designs. The engineer should operate independently, contribute deep technical expertise, and deliver highquality signoff packages in a fastpaced environment.

Key Responsibilities:

Develop and execute formal verification plans for IPlevel and subsystem designs.

Write highquality SVA/PSL properties and build complete formal environments.

Perform property proofs, coverage closure, abstraction modeling, and over/underconstraint analysis.

Debug counterexamples and rootcause design issues.

Provide regular reports, documentation, and formal sign-off deliveries.

Collaborate with Verification lead, RTL designers, and simulation teams to ensure design correctness.

Required Skills & Experience:

4 -20 years of handson experience in Formal Property Verification (FPV).

Strong proficiency in SystemVerilog Assertions (SVA) and formal tools (Jasper Gold, or any other equivalent formal tool).

Solid understanding of RTL design, microarchitecture, FSMs, clock/power domains, and interface protocols (AMBA AXI/APB/AHB).

Demonstrated experience with abstraction, COI analysis, vacuity checks, and formal completeness metrics.

Excellent debugging and analytical problemsolving skills.

Preferred Skills:

Experience with multilayer buses/ bus interconnects.

Knowledge of scripting languages (Python, Perl, TCL).

Engagement Expectations:

Work independently with minimal supervision.

Provide weekly status updates and maintain reproducible formal environments.

Deliver complete formal signoff packages as per project timelines.

Adhere to all confidentiality, documentation, and security protocols.

Working from office.