Formal Verification Director

Mulya Technologies; Bengaluru; On-site; INR 6,000,000 - 12,000,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks a Director of Formal Verification to steer the verification strategy for PCIe, CXL, Ethernet, UCIe, and UALink. You will set methodologies, act as the technical authority, and drive reliability across AI infrastructure connectivity products powering data centers worldwide.

Lead FV teams, mentor engineers, deliver testplans, and collaborate with RTL design to ensure high quality, scalable solutions.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, CS or related field.
• 15+ years in formal verification or 18+ years in traditional design with formal focus.
• Strong SystemVerilog/Verilog proficiency and hardware verification knowledge.
• Advanced scripting in Python or Perl for automation.
• Ability to manage multiple high-impact tasks in a fast-paced environment.
• Cross-functional collaboration and leadership across distributed teams.

Responsibilities

• Define and evolve formal verification strategy across product lines (PCIe, CXL, Ethernet, UCIe, UALink).
• Serve as technical authority on formal verification; guide design quality and risk mitigation.
• Represent the company in industry forums, standards bodies, and conferences.
• Drive cross-functional collaboration to influence technical direction.
• Develop FV test plans; collaborate with design teams on RTL assertions and testbenches.
• Identify key logic components and properties for correctness; implement models and checks.
• Apply complexity-reduction techniques with EDA tools to achieve convergence.
• Develop scripts to boost FV productivity; mentor engineers across sites.

Skills

Jasper (Jaspergold)

VCFormal (VC Formal)

PCIe

UCIe

Ethernet

UAL (UALink)

CXL

400G

800G

1600G

Python

Perl

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Bachelor's degree in Computer Science

Master's or PhD in Electrical Engineering or Computer Science

Tools

Synopsys VCFormal

Cadence JasperGold

Job description

Director, Formal Verification

Top30 Semiconductor Organization in the world

Bangalore

Overview

We are seeking a Director, Formal Verification to join our world-class engineering team. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution.

In this highly strategic role, you'll serve as technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide.

Key Responsibilities

• Strategic Leadership & Methodology Development
• Define and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocols
• Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality
• Represent us in industry forums, standards bodies, and technical conferences as a thought leader in formal verification
• Drive cross-functional collaboration to influence technical direction across the organization
• Technical Execution & Innovation
• Develop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs
• Apply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depth
• Develop and maintain scripts to enhance FV productivity and streamline verification processes
• Team Development & Cross-Functional Partnership
• Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback
• Prepare and deliver customer meetings and executive presentations with minimal supervision

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field
• 15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specialization
• Strong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verification
• Advanced scripting abilities with Python or Perl for automation and productivity enhancement
• Proven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervision
• Strong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensus
• Entrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standards

Preferred Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verification
• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold
• Experience with both bug hunting and static proof verification techniques
• Familiarity with automating formal verification workflows within a CI/CD environment
• Deep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALink
• Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)
• Patents or publications in formal verification or hardware verification methodologies
• Track record of recruiting, mentoring, and developing formal verification talent across distributed teams

Skills

• Jasper (Jaspergold)
• VCFormal (VC Formal )
• PCIe
• UCIe
• Ethernet
• UAL (UALink)
• CXL
• 400G
• 800G
• 1600G
• Python
• Perl

Contact:Uday

Mulya

Technologies

[e-mail]