Sr. Formal Verification Engineer

Baya Systems; Bengaluru; Vor Ort; INR 1.000.000 - 1.500.000; Vollzeit

Zusammenfassung

A technology company in Bengaluru is seeking an experienced Formal Verification specialist to join their team. The role requires strong proficiency in SystemVerilog and scripting abilities, with at least 6-7 years of industry experience. This position involves developing formal verification test plans, implementing models and assertions, and collaborating closely with design teams. The ideal candidate has familiarity with formal verification tools and is ready to work onsite in Whitefield.

Qualifikationen

• At least 6-7 years of industry experience in formal verification.
• Strong proficiency in formal verification tools.
• Good understanding of RTL design and verification processes.

Aufgaben

• Develop FV test plans and collaborate with design teams.
• Implement formal verification models and assertions.
• Enhance FV productivity through script development.
• Participate in design reviews and optimize design quality.

Kenntnisse

SystemVerilog/Verilog

Scripting with Python or Perl

Tools

Synopsys VCFormal

Cadence JasperGold

Jobbeschreibung

Overview

Baya Systems is seeking an experienced Formal Verification specialist to join the DV team in Bengaluru. This position is full onsite in the Whitefield office. We are looking for at least 6/7 years of industry experience.

For those interested, please apply to the job posting below or contact: Manager, Talent Acquisition.

Responsibilities

• Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications.
• Identify key logic components and critical micro-architectural properties essential for ensuring design correctness.
• Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs.
• Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth.
• Develop and maintain scripts to enhance FV productivity and streamline verification processes.
• Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels.
• Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, and area (PPA) metrics based on formal analysis feedback.

Qualifications

• Strong proficiency in SystemVerilog/Verilog.
• Good scripting abilities with Python or Perl.

Preferred Experience

• Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold.
• Experience with both bug hunting and static proof verification techniques.
• Familiarity with automating formal verification workflows within a CI/CD environment.

Job Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Job function: Engineering and Other
• Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, and Software Development

Locations: Onsite in Bengaluru (Whitefield).