Staff Engineer

SiFive India Private Limited

Ahmedabad District

On-site

INR 1,200,000 - 1,800,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

SiFive India Private Limited seeks a Formal Verification Engineer to spearhead validation processes for critical interconnect components. The ideal candidate will possess over 7 years of experience in formal verification, particularly with RTL designs. Key responsibilities include developing rigorous verification plans, analyzing proof convergence, and collaborating with design teams to enhance verification methodologies.

This role demands strong communication and problem-solving skills, alongside a solid grounding in SystemVerilog. A successful background check and authorization for access to export-controlled technologies is required. Join a diverse and inclusive workplace at SiFive.

Qualifications

  • 7+ years of experience with a degree in Electrical Engineering or related field.
  • Strong experience in formal verification of RTL designs.
  • Solid knowledge of SystemVerilog and SVA.

Responsibilities

  • Own formal verification of NoC and interconnect blocks.
  • Develop verification plans and formal property sets.
  • Analyze proof convergence and coverage gaps.

Skills

Formal verification of RTL designs
SystemVerilog
Problem-solving skills
Communication skills
Scripting in Python

Education

BS/MS in Electrical Engineering or Computer Engineering

Tools

SystemVerilog Assertions (SVA)

Job description

Key Responsibilities
  • Own formal verification of NoC and interconnect blocks such as crossbar, arbiter, bus-blocker, on-ramp, off-ramp, and related fabric components
  • Develop verification plans and formal property sets for block-level and subsystem-level verification
  • Write SystemVerilog Assertions (SVA), assumptions, cover properties, and protocol checks
  • Build and maintain reusable formal verification environments, checkers, and scoreboarding infrastructure where needed
  • Drive bug hunting, root-cause analysis, and closure of formal counterexamples with design and architecture teams
  • Analyze proof convergence, over-constraint/under-constraint issues, and coverage gaps
  • Collaborate with design, architecture, and simulation/emulation teams to ensure complete verification closure
  • Contribute to verification methodology improvements for scalable interconnect verification
Required Qualifications
  • 7+ years of experience with BS/MS in Electrical Engineering, Computer Engineering, or related field
  • Strong experience in formal verification of RTL designs
  • Solid knowledge of SystemVerilog and SVA
  • Experience verifying interconnects, NoCs, coherent fabrics, or complex SoC subsystems
  • Good understanding of common NoC building blocks such as arbiters, routers, crossbars, flow control, buffering, and protocol adapters
  • Experience with debugging formal failures, constraint issues, and proof complexity
  • Strong problem-solving and communication skills
Preferred Qualifications
  • Experience with coherent interconnect protocols and memory subsystem verification
  • Experience with performance-oriented verification, simulation, or emulation
  • Familiarity with clock-domain crossing, reset verification, deadlock/livelock checks, and end-to-end data integrity properties
  • Scripting experience in Python, Perl, or Tcl for automation and flow improvements
  • Experience defining verification strategy and signoff criteria for complex IP/subsystems
What Success Looks Like
  • High-quality formal verification plans and property suites for NoC blocks
  • Efficient proof closure with meaningful coverage
  • Early detection of corner-case bugs in arbitration, routing, buffering, and protocol handling
  • Reusable methodology that scales across multiple interconnect components
Nice-to-Have Domain Experience
  • Crossbar and arbiter verification
  • Bus-blocker and safety/security-oriented interconnect logic
  • On-ramp/off-ramp style ingress/egress fabric components
  • Multi-clock and subsystem integration challenges in NoC environments
Additional Information
  • This position requires a successful background and reference checks and satisfactory proof of your right to work in: India
  • Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Staff Engineer
Staff Engineer

SiFive, Inc. • Ahmedabad District

On-site
INR 1,500,000 - 2,000,000
Staff Engineer - Formal Verification
Staff Engineer - Formal Verification

SiFive India Private Limited • Bengaluru

On-site
INR 2,500,000 - 3,500,000
Senior IP Verification Engineer(IOMMU-N)
Senior IP Verification Engineer(IOMMU-N)

SiFive India Private Limited • Bengaluru

On-site
INR 1,000,000 - 1,500,000
Senior Staff Verification Engineer For Worldguard
Senior Staff Verification Engineer For Worldguard

SiFive India Private Limited • Bengaluru

On-site
INR 2,500,000 - 3,500,000
Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)
Engineer / Staff / Sr. Staff Engineer - CPU Verification (RAS)

SiFive India Private Limited • Hyderabad

On-site
INR 800,000 - 1,200,000
Staff Engineer - Formal Verification
Staff Engineer - Formal Verification

SiFive, Inc. • Bengaluru

On-site
INR 1,200,000 - 1,600,000
Formal Verification Director
Formal Verification Director

Mulya Technologies • Bengaluru

On-site
INR 6,000,000 - 12,000,000
CPU Design Verification Engineer
CPU Design Verification Engineer

SiFive India Private Limited • Hyderabad

On-site
INR 800,000 - 1,500,000
Equal opportunity employer
Inclusive work environment
Formal Verification Engineer
Formal Verification Engineer

ACL Digital • Bengaluru

Hybrid
INR 4,000,000 - 8,000,000
CPU Design Verification Engineer
CPU Design Verification Engineer

SiFive, Inc. • Hyderabad

On-site
INR 1,200,000 - 1,800,000