Senior layout Engineer – DPG Layout

1840 Micron Tech. OP India LLP; New Delhi; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Micron Technology, Inc. in India is seeking an experienced analog/layout engineer to implement the design and physical layout of analog/mixed-signal blocks and support full‑chip integration.

You will own block‑level layout execution with emphasis on quality and turnaround time, and you will use AI tools to automate repetitive tasks and refine scripts for layout and verification. The role requires strong problem‑solving skills and collaboration with senior engineers.

Qualifications

• 3+ years of analog/custom layout design in advanced CMOS process.
• Hands-on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS.
• Experience in layout of critical analog and mixed-signal blocks (Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps).
• Understanding of analog layout fundamentals (matching, symmetry, electromigration, latch-up, IR-drop, coupling, crosstalk, parasitics).
• Experience developing or applying AI-driven automation to improve layout tasks.

Responsibilities

• Implement the design and physical implementation of analog, mixed-signal, custom digital blocks and support full-chip integration.
• Own block-level layout execution with focus on quality, turnaround time and design intent.
• Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks.
• Deliver on-time, high-quality block-level layouts under guidance from senior engineers.
• Use prompt-based AI tools to generate or refine SKILL/Python/TCL scripts, automate repetitive tasks.
• Support custom and digital layout integration using semicustom tools to accelerate ECOs and updates.
• Collaborate with Design, Verification, CAD, and senior layout engineers; communicate status and risks.
• Review sub-block layouts and share techniques within the team.

Skills

Analog layout

Cadence Virtuoso

AI-driven automation

Layout verification

Problem solving

Digital/analog mix

High‑quality block layouts

Tools

Calibre DRC/LVS

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

Implement the design and physical implementation of analog, mixed‑signal, custom digital blocks and support full‑chip integration, using a combination of traditional layout expertise.

Own block‑level layout execution with strong focus on quality, turnaround time and design intent.

Perform layout verification activities, including DRC, LVS, Antenna checks, Yield and quality checks.

Deliver on‑time, high‑quality block‑level layouts under the guidance from senior engineers.

Use prompt‑based AI tools to Generate or refine SKILL/Python/TCL scripts, automate repetitive layout and verification tasks to reduce manual effort and improve layout consistency.

Support custom and digital layout integration, using semicustom tools to accelerate ECOs, alignment, and integration‑level updates.

Collaborate closely with Design, Verification, CAD, and senior layout engineers, clearly communicating layout status and risks.

Assist in reviewing sub‑block layouts from engineers developing their skills and share helpful techniques within the team.

Job Requirements

• 3+ year experience in analog/custom layout design in advanced CMOS process.
• Hands‑on experience with Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, including ownership of verification and closure for assigned blocks.
• Experience in layout of critical analog and mixed‑signal blocks like Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps.
• Exposure to memory layout environments, including DRAM, SRAM, CAM or OTP is desirable.
• Solid understanding of analog layout fundamentals, including Matching and symmetry techniques electromigration, latch‑up, IR‑drop, Coupling, crosstalk and parasitic effects.
• Understanding of layout impact on circuit performance, including speed, capacitance, power, and area.
• Ability to interpret design constraints and translate them into robust, manufacturable layouts.
• Hands‑on experience in developing or applying AI‑driven automation and AI‑assisted methodologies to improve efficiency and quality of physical layout tasks.
• Strong problem‑solving skills in physical layout verification and debug.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.