DV Architect

Intellics Global Services; Hyderabad, Chennai, Bengaluru; Hybrid; INR 4,000,000 - 7,000,000; Full time

Job summary

Intellics Global Services seeks a DV Architect to define verification strategies and architect scalable UVM environments for subsystem and SoC designs. You will own coverage closure and verification signoff across multiple teams in an ASIC/SoC setup.

You will lead DV teams, drive constrained-random, formal and power-aware verification, and establish regression and automation infrastructure. Collaboration with RTL, DFT, PD and firmware is essential.

Qualifications

• Seasoned verification lead with 15+ years in ASIC/SoC verification.
• Expertise in SystemVerilog, UVM, SVA and coverage-driven verification.
• Experience leading DV teams and serving as technical escalation point.

Responsibilities

• Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
• Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
• Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
• Establish regression, automation and quality metrics infrastructure.
• Lead technical reviews of test plans, testbench architecture and coverage closure.
• Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

Skills

Leadership

DV management

Regression management

Communication

Problem solving

Tools

SystemVerilog

UVM

SVA

Coverage-driven verification

UPF/power-aware verification

Job description

Role & responsibilities

JOB DESCRIPTION

DV Architect

Experience

15+ years

Location

hyderabvad, Bangalore, chennai,pune,kochi

Domain

ASIC / SoC Turnkey Silicon

Employment

Full-time

The Role

Define verification strategy and architect scalable UVM environments for subsystem and SoC designs, owning coverage closure and verification signoff.

What You Will Do

• Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
• Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
• Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
• Establish regression, automation and quality metrics infrastructure.
• Lead technical reviews of test plans, testbench architecture and coverage closure.
• Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

What You Bring

• 15+ years in ASIC/SoC verification, with ownership of subsystem and chip-level verification through tape-out.
• Expert SystemVerilog, UVM, SVA and coverage-driven verification.
• Experience leading DV teams and being the technical escalation point.
• Strong with high-speed and bus protocols such as PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe.
• Hands‑on with regression management, debug and gate‑level / power‑aware simulation.
• Scripting in Python, Perl or Shell.

Good to Have

• Formal verification and emulation / FPGA prototyping
• Hardware/software co-verification
• Post-silicon bring‑up exposure