Technical Lead, Design Verification

PulseWaveSemi; India; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

The company PulseWaveSemi is seeking a Technical Lead in Design Verification, located in Ahmedabad, Gujarat. The role requires a strong background in leading DV teams, with proven experience in UVM test benches and debugging complex issues. You will provide leadership and innovative methodologies to enhance project verification and efficiency.

Applicants should hold a relevant engineering degree and have at least 10 years of experience in design verification. The position offers opportunities to architect advanced verification solutions in a collaborative environment.

Qualifications

• 10+ years of relevant experience in design verification.
• Experience leading a DV team of 5-10 engineers.
• Strong experience in debugging complex issues.

Responsibilities

• Provide technical and project leadership to a team of DV engineers.
• Develop innovative verification methodologies.
• Drive complete verification from testplan development to coverage sign-off.

Skills

Leadership

UVM test benches

Debugging

Scripting languages (Python, Shell, TCL, Perl)

Project Planning

Education

B.E/B.Tech or M.E./M.Tech in Electronics/Electronics & Communication/Microelectronics/Electrical Engineering

Tools

UCI

PCIe

DDR

NoC (Fabric)

Job description

• Designation : Technical Lead, Design Verification
• Location : Ahmedabad (Gujarat)
• Experience Required : 10+ Years of relevant experience
• Qualification : B.E/B.Tech or M.E./M.Tech in Electronics, Electronics & Communication, Microelectronics, Electrical Engineering. Other Science graduates would be considered if they have relevant experience

What You’ll Need

• Experience leading DV team comprising 5-10 engineers.
• Hands on experience on IP, Subsystem and SoC Design Verification experience
• Experience UVM test benches and Scoreboard development.
• Work with the team to improve DV methodology and infrastructure
• Strong experience in debugging complex issues
• Sound expertise in Testplan, Project Planning and Testbench Architecture
• Experience working on UCI, PCIe, DDR, NoC (Fabric) is an added advantage.
• Experience in GLS is a plus.

What you will be doing

Provide technical and project leadership to a team of DV engineers. Your responsibilities include architecting and bringing up advanced UVM test benches and scoreboards for complex designs, coupled with comprehensive project planning and task scheduling. You will drive complete verification of project ownership, from testplan development to final coverage sign-off. A key aspect of this role is developing and implementing innovative verification methodologies to improve overall effectiveness and efficiency. Proven proficiency in scripting languages such as Python, Shell, TCL, or Perl is a must.