ASIC SOC Design Verification - System Verilog;UVM

HCL Technologies Limited; Bengaluru; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

HCL Technologies Limited in Bengaluru seeks a Design Verification Engineer to lead verification for our ASIC and SoC programs. This senior role requires deep expertise in verification methodologies and a proven ability to drive large-scale verification projects from strategy to sign-off.

You will architect robust UVM-based verification environments, work with simulators, formal verification tools and debuggers, mentor junior DV engineers, and influence the verification roadmap in partnership

Qualifications

• 6+ years of DV experience on ASIC/SoC designs.
• Hands-on with UVM, SystemVerilog, Verilog/VHDL, and Assertions.
• Experience leading verification teams and projects.
• Strong scripting skills in Perl/Python/Tcl.
• Excellent communication and leadership abilities.

Responsibilities

• Develop end-to-end verification strategy for complex ASIC/SoC programs.
• Architect and develop UVM-based verification environments and testbenches.
• Apply UVM, Formal Verification, and Assertions.
• Work with simulators, formal tools, and debuggers.
• Debug failures, perform root-cause analysis, and partner with design teams.
• Mentor DV engineers and drive best practices.
• Influence the verification roadmap and technical decisions.

Skills

UVM

SystemVerilog

Verilog/VHDL

Assertions

Digital design

Perl/Python/Tcl

Leadership

Communication

Education

Master's degree preferred

Bachelor's degree in Electrical/Computer Eng

Tools

Simulators

Formal tools

Debuggers

Job description

Locations: Chennai | Bangalore | Hyderabad

About the Role

HCLTech is looking for a highly accomplished Design Verification Engineer (DV) to lead verification for our most critical ASIC and SoC programs. This is a senior technical leadership role that demands deep expertise in verification methodologies and a proven ability to drive large‑scale verification projects from strategy to sign‑off.

If you are passionate about building next‑generation silicon with world‑class quality, this opportunity is for you.

• end‑to‑end verification strategy for complex ASIC/SoC programs
• Architect and develop robust UVM-based verification environments and testbenches
• Leverage advanced verification methodologies—UVM, Formal Verification, Assertions
• Work hands‑on with industry‑leading tools (simulators, formal tools, debuggers)
• Debug complex failures, perform root‑cause analysis, and partner with design teams
• Drive code quality, enforce best practices, and participate in design/code reviews
• Mentor and guide junior DV engineers; foster a high‑performance technical culture
• Stay ahead of emerging verification technologies, tools, and methodologiesInfluence the verification roadmap and contribute to technical decision‑making

Qualifications

• Master’s (preferred) or Bachelor’s degree in Electrical/Computer Engineering
• 6+ years of experience in Design Verification for complex ASIC/SoC designs
• Hands‑on expertise with UVM, SystemVerilog, Verilog/VHDL, Assertions
• Deep understanding of digital design fundamentals
• Strong experience with simulators, formal verification tools, and scripting (Perl/Python/Tcl)
• Proven track record of leading verification teams and driving project success
• Excellent communication, leadership, analytical, and troubleshooting skills
• Ability to handle multiple priorities and deliver under aggressive timelines
• Competitive compensation aligned with your expertise
• Opportunity to lead verification of cutting‑edge semiconductor technologies
• Career growth into technical leadership and organization‑wide influence
• Dynamic and collaborative work culture
• Recognition and rewards for outstanding performance