Design Verification Architect

Wipro; Ernakulam, Hyderabad; Hybride; INR 6 000 000 - 9 000 000; Plein temps

Résumé du poste

Wipro invites an experienced Design Verification Architect to shape verification strategy for complex ASIC/SoC projects. The role demands leading DV teams, owning coverage closure, and signoff across subsystems and chips.

The candidate should excel in SystemVerilog, UVM, SVA, and coverage-driven approaches, with strong knowledge of PCIe, DDR/LPDDR, Ethernet, AMBA, and UCIe. Hybrid work across multiple locations is supported.

Qualifications

• 15+ years in ASIC/SoC verification with ownership of subsystem and chip-level verification through tape-out.
• Expert in SystemVerilog, UVM, and coverage-driven verification.
• Proven experience leading DV teams and acting as technical escalation point.
• Strong understanding of high-speed protocols (PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe).
• Hands-on regression management, debug and power-aware (UPF) / gate-level verification.

Responsabilités

• Define end-to-end verification strategy, plans, coverage models and signoff criteria.
• Architect reusable SystemVerilog/UVM testbenches and VIP at subsystem/SoC level.
• Drive constrained-random, assertion-based (SVA), formal and power-aware verification.
• Establish regression, automation and quality metrics infrastructure.
• Lead reviews of test plans, testbench architecture and coverage closure.
• Collaborate with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

Connaissances

SystemVerilog

UVM

SVA

Coverage-driven verification

DV team leadership

PCIe

DDR/LPDDR

Ethernet

AMBA/UCIe

Python scripting

Description du poste

Greetings from Wipro

We are pleased to share an exciting opportunity for the Design Verification Architect role at Wipro.

Role Details

Requirement Name : Design Verification Architect

Experience:15 Years +

Work location : Bengaluru / Hyderabad / Kochi / Chennai / Any Location

Work Mode : Hybrid

Job Type: Full-Time with Wipro

JD

Define verification strategy and architect scalable UVM environments for subsystem and SoC designs, owning coverage closure and verification signoff.

What You Bring(Mandatory):

• 15+ years in ASIC/SoC verification, with ownership of subsystem and chip-level verification through tape-out.
• Expert SystemVerilog, UVM, SVA and coverage-driven verification.
• Experience leading DV teams and being the technical escalation point.
• Strong with high-speed and bus protocols such as PCIe, DDR/LPDDR, Ethernet, AMBA, UCIe.
• Hands-on with regression management, debug and gate-level / power-aware simulation.
• Scripting in Python, Perl or Shell.

What You Will Do:

• Define the end-to-end verification strategy, plans, coverage models and signoff criteria.
• Architect reusable, scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level.
• Drive constrained-random, assertion-based (SVA), formal, power-aware (UPF) and gate-level verification.
• Establish regression, automation and quality metrics infrastructure.
• Lead technical reviews of test plans, testbench architecture and coverage closure.
• Work with RTL, DFT, PD and firmware teams; support emulation and post-silicon debug.

Good to Have :

• Formal verification and emulation / FPGA prototyping
• Hardware/software co-verification
• Post-silicon bring-up exposure