DFT Engineers

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd in Bengaluru is seeking a skilled DFT engineer to execute and support design-for-test activities, including scan insertion, ATPG, and OCC integration. You will debug DRC, test coverage, and simulations across the DFT flow and collaborate with cross-functional teams to resolve testability issues.

The role requires strong DFT fundamentals, experience with SSN, IJTAG, ICL, and PDL frameworks, and a structured, analytical approach to debugging complex patterns and fault

Qualifications

• Deep knowledge of DFT fundamentals: ATPG, scan architecture, and OCC.
• Experience with DRC debug, test coverage, and simulation debug.
• Exposure to SSN, IJTAG, ICL, and PDL frameworks.
• Ability to analyze complex issues and provide structured debug solutions.

Responsibilities

• Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
• Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
• Analyze and resolve issues related to testability, fault coverage, and pattern generation
• Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
• Collaborate with cross-functional teams to ensure smooth DFT integration and issue
• Contribute to continuous improvement of DFT flows, methodologies, and debug

Skills

DFT fundamentals

Debugging & analysis

SSN/IJTAG/ICL/PDL

Structured problem solving

Job description

NOTE: Immediate candidates are preferred.

Key Responsibilities

• Execute and support Design-for-Test (DFT) activities including scan insertion, ATPG, and OCC integration
• Perform DRC debug, test coverage analysis, and simulation debug across various stages of the DFT flow
• Analyze and resolve issues related to testability, fault coverage, and pattern generation
• Work with advanced DFT methodologies including SSN, IJTAG, ICL, and PDL handling
• Collaborate with cross-functional teams to ensure smooth DFT integration and issue
• Contribute to continuous improvement of DFT flows, methodologies, and debug

Required Skills & Experience

• Strong understanding of DFT fundamentals including ATPG, scan architecture, and OCC
• DRC debug, Coverage debug,Simulation debug (various modes and scenarios)
• Exposure to SSN, IJTAG, ICL, and PDL frameworks
• Ability to analyze complex issues and provide structured debug solutions