DFT Engineer - Hyderabad

Tecquire Solutions Pvt Ltd; Hyderabad; On-site; INR 800,000 - 1,400,000; Full time

Job summary

Tecquire Solutions Pvt Ltd is looking for a hands-on DFT Engineer / Senior DFT Engineer in Hyderabad, India. The ideal candidate will possess 3–6 years of DFT experience and is expected to independently manage end-to-end DFT tasks, contributing to architecture definition, execution of scan insertion, and supporting DFT signoff. Strong expertise in DFT tools and debugging skills are essential for success in this role, and the company emphasizes collaboration with design and manufacturing teams.

Qualifications

• 3–6 years of hands-on DFT experience with block/SoC-level implementation.
• Ability to drive DFT tasks independently from insertion to sign-off.
• Strong expertise in scan, ATPG, and DFT DRC.

Responsibilities

• Contribute to DFT architecture definition.
• Drive RTL testability and support trade-offs.
• Execute scan insertion and DFT DRC closure.
• Run ATPG and pattern optimization.
• Support DFT signoff and debug DFT issues.

Skills

DFT implementation

Scan technology

ATPG

Debugging skills

Scripting (Tcl/Perl/Python)

Tools

Cadence DFT tools

Siemens (Mentor) DFT tools

Job description

We are seeking a hands‑on DFT Engineer / Senior DFT Engineer to drive DFT implementation for complex SoCs across the design cycle. This role requires strong execution capability, good technical judgment, and the ability to work independently on block/SoC‑level deliverables while collaborating closely with design, PD, validation, and manufacturing teams.

The ideal candidate is comfortable owning DFT tasks end‑to‑end (within a module or subsystem), with a strong focus on coverage, quality, and timely execution.

Responsibilities

• Contribute to DFT architecture definition at block/subsystem level (scan, compression, MBIST, LBIST basics, boundary scan, test access)
• Drive RTL testability and support trade‑offs across coverage, test time, power, and area
• Execute scan insertion, stitching, and DFT DRC closure
• Run ATPG (stuck‑at, transition, path delay), compression, and pattern optimization
• Support DFT signoff: coverage, pattern volume, test time, and basic power/timing considerations
• Debug DFT issues across RTL, synthesis, P&R, and gate‑level simulations
• Generate and analyze ATPG patterns; identify and close coverage gaps
• Support silicon bring‑up, failure analysis, and debug of scan/BIST/tester issues
• Work with ATE/manufacturing teams for pattern validation and yield improvement
• Drive DFT ECOs and support methodology improvements

Qualifications

• 3–6 years of hands‑on DFT experience with ownership of block/SoC‑level DFT implementation
• Able to independently drive DFT tasks from insertion to sign‑off with minimal supervision
• Strong expertise in scan (stitching/compression), ATPG, DFT DRC, MBIST (with repair), LBIST basics, JTAG/Boundary Scan (IEEE 1149.1), and low‑power DFT
• Good debugging skills across DFT insertion, ATPG patterns, and coverage closure
• Proficient in Cadence / Siemens (Mentor) DFT tool flows
• Strong scripting skills (Tcl/Perl/Python) for automation and debug
• Solid understanding of RTL, Lint/CDC, low‑power intent, and ASIC design flow
• Ability to collaborate effectively with RTL, PD, and STA teams to close DFT and coverage issues

Soft Skills

• Strong ownership mindset with ability to independently drive assigned DFT deliverables
• Structured debugging approach across RTL, ATPG, scan/BIST, and silicon issues
• Clear communication of coverage metrics, risks, and progress
• Ability to manage multiple deliverables in a fast‑paced environment
• Team‑oriented mindset with willingness to learn and contribute