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Acesoft Labs in Hyderabad is seeking a DFT Engineer with 4-6 years of hands-on experience in Design for Test for SoC designs. You will drive DFT implementations at RTL and gate levels, including scan insertion, MBIST/LBIST, and boundary scan.
Collaborate with cross-functional teams across STA, synthesis, LEC, CLP, and functional verification to ensure robust testability. Proficiency with DFT tools from Siemens, Synopsys, and Cadence is essential.
Notice Period: 30 Days
Position: DFT Engineer
Looking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in Hyderabad!