DFT Engineer

Acesoft Labs

Hyderabad

On-site

INR 1,200,000 - 2,200,000

Full time

14 days+
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Job summary

Acesoft Labs in Hyderabad is seeking a DFT Engineer with 4-6 years of hands-on experience in Design for Test for SoC designs. You will drive DFT implementations at RTL and gate levels, including scan insertion, MBIST/LBIST, and boundary scan.

Collaborate with cross-functional teams across STA, synthesis, LEC, CLP, and functional verification to ensure robust testability. Proficiency with DFT tools from Siemens, Synopsys, and Cadence is essential.

Qualifications

  • 4–6 years of experience in Design for Test (DFT) for SoC designs.
  • Experience with RTL and Gate-level DFT concepts such as scan insertion, MBIST/LBIST, and boundary scan.

Responsibilities

  • Drive DFT implementations at RTL and gate level for SoC designs, including scan insertion, MBIST, LBIST, and boundary scan.
  • Generate and validate ATPG patterns through simulation.
  • DFT verification using RTL and gate-level simulations.
  • Collaborate with cross-functional teams across STA, synthesis, LEC, CLP, and functional verification.

Skills

Verilog or SystemVerilog
VHDL
C/C++
TCL
Perl
Python

Tools

Siemens
Synopsys
Cadence

Job description

We are hiring DFT Engineer | Hyderabad

Notice Period: 30 Days

Position: DFT Engineer

Looking for passionate professionals with 4 to 6 years of experience in Design for Test (DFT) to join our growing team in Hyderabad!

Key Responsibilities:
  • Drive innovative DFT implementation at RTL and Gate level for SoC designs at both hard macro and chip top level, including:
    Scan insertion
    MBIST (Memory BIST)
    LBIST (Logic BIST)
    Boundary Scan
  • Generate and validate ATPG patterns through simulation
  • DFT verification using RTL and Gate-level simulations
  • Collaborate with cross-functional teams across:
    Static Timing Analysis (STA)
    Synthesis
    Logic Equivalence Check (LEC)
    CLP
    Functional Verification & Validation
Tool Proficiency:
  • Experience with DFT tools from:
    Siemens
    Synopsys
    Cadence
Technical Skills:
  • Strong coding skills in:
    Verilog, VHDL
    C/C++
    TCL, Perl, Python
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