DFT Engineer

Cyient Limited; Hyderabad; Presencial; INR 900 000 - 1 500 000; Tempo integral

Resumo da oferta

Cyient Limited is seeking DFT Engineers to work on ASIC controller projects, focusing on gate-level structural testing and DFT implementation. The role involves scan insertion, ATPG, and JTAG boundary scan concepts, with cross-team collaboration to improve testability and robust validation using industry-standard DFT tools.

Candidates should have hands-on experience in scan insertion and ATPG, plus a solid grounding in memory-based systems.

Qualificações

• Strong hands-on experience in Scan Insertion and ATPG.
• Good understanding of DFT concepts and methodologies.
• Knowledge of JTAG (boundary scan concepts).
• Exposure to memory-based system architectures.
• Experience with DFT tools (any standard tools).

Responsabilidades

• Perform DFT activities for ASIC controller designs.
• Execute scan IP insertion and scan stitching.
• Work on ATPG (Automatic Test Pattern Generation).
• Collaborate with design teams for testability improvements.
• Support gate-level structural testing workflows.
• Utilize industry tools for DFT implementation and validation.

Conhecimentos

Scan Insertion

ATPG

DFT concepts

JTAG boundary scan

Memory-based systems

DFT tools

Team collaboration

Industry-standard tools

Formação académica

Bachelor’s/Master’s degree in Electronics/Electrical/Computer Engineering or equivalent

Ferramentas

Cadence DFT tools

Synopsys Design Compiler (DC)

ATPG/DFT tool suites

Scan/insertion tools

JTAG debugging tools

Descrição da oferta de emprego

Job Description:

We are hiring DFT Engineers for ASIC controller projects, focusing on gate-level structural testing and Design for Testability (DFT) implementation. The ideal candidate will have hands‑on expertise in scan insertion and ATPG, along with a good understanding of memory-based systems.

Key Responsibilities

• Perform DFT activities for ASIC controller designs
• Execute scan IP insertion and scan stitching
• Work on ATPG (Automatic Test Pattern Generation)
• Collaborate with design teams for testability improvements
• Support gate‑level structural testing workflows
• Utilize industry tools for DFT implementation and validation

Required Skills

• Strong hands‑on experience in Scan Insertion and ATPG
• Good understanding of DFT concepts and methodologies
• Knowledge of JTAG (boundary scan concepts)
  • Note: Implementation expertise is not mandatory
• Exposure to memory‑based system architectures
• Experience with DFT tools (any standard tools are acceptable)

Preferred Technical Expertise

• Familiarity with Cadence DFT tools
• Experience with Synopsys Design Compiler (DC) or equivalent
• Ability to work across tools (Cadence/Synopsys preferred but not mandatory)

Education

• Bachelor’s/Master’s degree in Electronics/Electrical/Computer Engineering or equivalent

Additional Notes

• This is a gate‑level structural testing role (RAM/memory BIST experience is not mandatory)
• Candidates should be flexible to work with available DFT toolchains