DFT (Design for Testability) Engineer

Gtc Informatics Private Limited; India; A distancia; INR 1.200.000 - 2.400.000; Jornada completa

Descripción de la vacante

GTC Informatics Private Limited is seeking experienced DFT engineers for ASIC and SoC projects across India. Roles are open on both full-time and contract bases, with quick joining encouraged.

The team defines DFT architectures, performs scan insertion, ATPG, MBIST, and JTAG/boundary scan, and collaborates with design and physical design teams to achieve DFT timing closure. Candidates should have 4–10 years of DFT experience, hands-on tool proficiency (Tessent, TetraMAX, Modus), and strong

Formación

• 4–10 years of experience in DFT for ASIC/SoC.
• Hands-on experience with scan insertion, ATPG, MBIST and JTAG.
• Experience with tools such as Siemens Tessent, Synopsys TetraMAX/DFT Compiler or Cadence Modus.
• Good understanding of fault models (stuck-at, transition) and test coverage.
• Knowledge of Verilog and of the synthesis and STA flow.
• Good debugging and communication skills.

Responsabilidades

• Define and implement DFT architecture for ASIC/SoC designs
• Carry out scan insertion, compression and ATPG pattern generation
• Implement MBIST, LBIST and JTAG/boundary scan
• Run pattern simulations (zero-delay and timing) and debug failures
• Improve test coverage and work with design and physical design teams on DFT timing closure
• Support silicon test, bring-up and ATE debug with test teams

Conocimientos

DFT

ATPG

MBIST

JTAG

Verilog

Synthesis

STA flow

Herramientas

Siemens Tessent

Synopsys TetraMAX/DFT Compiler

Cadence Modus

Descripción del empleo

About the Role:

GTC Informatics Private Limited is hiring experienced DFT Engineers for ASIC and SoC projects across India. These positions are open on both a full-time and contract basis, depending on client and project requirements. Experienced candidates who can join quickly are encouraged to apply.

Location : PAN INDIA

Roles & Responsibilities:

• Define and implement DFT architecture for ASIC/SoC designs
• Carry out scan insertion, compression and ATPG pattern generation
• Implement MBIST, LBIST and JTAG/boundary scan
• Run pattern simulations (zero-delay and timing) and debug failures
• Improve test coverage and work with design and physical design teams on DFT timing closure
• Support silicon test, bring-up and ATE debug with test teams

Required Skills & Experience:

• 4-10 years of experience in DFT for ASIC/SoC
• Hands-on experience with scan insertion, ATPG, MBIST and JTAG
• Experience with tools such as Siemens Tessent, Synopsys TetraMAX/DFT Compiler or Cadence Modus
• Good understanding of fault models (stuck-at, transition) and test coverage
• Knowledge of Verilog and of the synthesis and STA flow
• Good debugging and communication skills

Good to Have:

• Experience with scan compression (EDT/DFTMAX)
• Silicon bring-up and ATE debug experience
• ing skills in Tcl, Perl or Python