DFT (Design for Testability) Engineer

Central Business Solutions, Inc; Bengaluru; Sur place; INR 1 200 000 - 2 400 000; Plein temps

Résumé du poste

Central Business Solutions, Inc. is seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage and silicon quality across advanced nodes.

You will implement scan insertion, ATPG, MBIST/LBIST, and JTAG solutions while collaborating with RTL teams to embed DFT-friendly practices early in the design cycle. 5–8 years of DFT experience preferred.

Qualifications

• 5–8 years of DFT experience in ASIC/SoC design flow.
• Hands-on ATPG, scan insertion and fault coverage analysis.
• Experience with MBIST/LBIST architectures and JTAG implementations.
• Familiarity with industry DFT tools and TCL scripting is a plus.

Responsabilités

• Implement scan insertion, ATPG pattern generation, and fault coverage analysis for digital designs.
• Design and integrate MBIST and LBIST architectures.
• Develop and validate JTAG/boundary scan (IEEE 1149.1) implementations.
• Collaborate with RTL teams to ensure DFT-friendly designs early in the cycle.
• Analyze test coverage reports and address coverage gaps.
• Support silicon bring-up and debug using DFT structures for yield analysis.
• Work with EDA tools (Synopsys TestMAX/DFTMAX, Cadence Modus, Mentor Tessent) for ATPG and BIST.
• Coordinate with foundry/test teams on ATE pattern conversion and correlation.

Connaissances

ASIC/SoC design flow

Scan/ATPG

MBIST/LBIST

JTAG

Verilog/SystemVerilog

fault simulation

Outils

Synopsys TestMAX/DFTMAX

Cadence Modus

Mentor Tessent

Description du poste

DFT (Design for Testability) Engineer

Role Summary

We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage, manufacturing yield, and silicon quality across advanced technology nodes.

Responsibilities

• Implement scan insertion, ATPG pattern generation, and fault coverage analysis for digital designs
• Design and integrate Memory BIST (MBIST) and Logic BIST (LBIST) architectures
• Develop and validate JTAG/boundary scan (IEEE 1149.1) implementations
• Collaborate with RTL design teams to ensure DFT-friendly design practices are followed early in the design cycle
• Analyze test coverage reports and work to close coverage gaps
• Support silicon bring-up and debug using DFT structures for yield analysis
• Work with EDA tools (Synopsys TestMAX/DFTMAX, Cadence Modus, Mentor Tessent) for ATPG and BIST implementation
• Coordinate with foundry/test teams on ATE (Automated Test Equipment) pattern conversion and correlation

Required Skills

ASIC/SoC design flow, Scan/ATPG, MBIST/LBIST, JTAG, Synopsys/Cadence/Mentor DFT tools, Verilog/SystemVerilog, fault simulation

Experience

5–8 years in DFT Engineer role with ATPG experience (Must).