DFT Design Engineer

Einfochips; Hyderabad, Secunderabad, Bengaluru; Sur place; INR 1 260 000 - 1 540 000; Plein temps

Résumé du poste

Einfochips is seeking a DFT engineer in Hyderabad to lead scan insertion, BIST/MBIST, ATPG, and IP test validation across timing paths. You will drive DFT planning and sign-off for advanced nodes, collaborating with cross-functional teams to ensure robust test coverage.

The ideal candidate has strong DFT fundamentals, scripting skills in Tcl/Perl/Shell, and hands-on experience with standard EDA flows for 28nm, 16nm, and 7nm technologies.

Qualifications

• Strong fundamentals on DFT and ASIC cycle.
• Proficient in Tcl, Perl, and Shell scripting.
• Hands-on experience with DFT implementation using standard EDA flows.
• Experience with latest technology nodes (28nm,16nm,7nm).

Responsabilités

• In charge of scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and pattern validation with/without timing, DFT mode timing analysis and sign-off.
• Develop and own a comprehensive DFT plan.
• Collaborate with DFT and cross-functional teams.
• Architect and implement Scan and built-in self-test solutions for devices in the field.

Connaissances

DFT fundamentals

ASIC/SoC knowledge

Tcl

Perl

Shell scripting

EDA flow experience

MBIST/ATPG

Formation

B.E./B.Tech in ECE/EE/VLSI

M.S./M.Tech is a plus

Description du poste

ROLE & RESPONSIBILITIES

• Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off.
• Be responsible for a comprehensive DFT plan.
• Incumbent to work with DFT and cross functional teams.
• To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field.

ESSENTIAL SKILLS & EXPERIENCE

• Strong fundamentals on DFT and ASIC cycle.
• Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player.
• Hands-on experience with DFT implementation using standard EDA and flow is a must.
• Experience on latest technology (28nm,16nm,7 nm)

EDUCATION BACKGROUND

• B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.