DFT Engineer

LanceSoft, Inc.; Chennai District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

LanceSoft, Inc. in Chennai is seeking a hands-on DFT/ATPG expert to drive ATPG coverage improvements and debug complex DFT issues for SoC/ASIC designs.

You will own scan chain and DFT insertion flows, work with MBIST, and collaborate with design teams to enhance fault coverage across silicon iterations. The ideal candidate has 3+ years of SoC/ASIC experience with DFT, strong troubleshooting skills, and hands-on experience with Cadence DFT tools and related flows.

Qualifications

• 3+ years of SoC/ASIC Digital Design with DFT experience.
• Hands-on ATPG experience and fault coverage improvements.
• ATPG pattern verification using no-timing and SDF-annotated simulations.
• Debugging simulation miscompares and root-cause analysis.
• Scan chain and DFT insertion knowledge; understanding MBIST.
• Strong problem-solving and systematic debugging skills.

Skills

SoC/ASIC DFT experience

ATPG

ATPG coverage

ATPG pattern verification

Debugging simulations

Scan chain insertion

DFT insertion flows

MBIST

Problem solving

Compression scan

LBIST

Advanced scan technologies

JTAG 1149.1/1149.6 / IEEE 1500 / 1687

Cadence DFT tools

Synthesis debugging

Verilog testbench debugging

Tools

Cadence DFT tools/flows

Job description

We’re looking for someone with strong hands-on experience in ATPG, scan, and DFT flows, with the ability to independently handle DFT tasks and debug complex issues.

Must Have:

• 3+ years of SoC/ASIC Digital Design with DFT experience
• Strong hands-on ATPG experience
• ATPG coverage analysis and fault coverage improvement
• ATPG pattern verification using no-timing and SDF-annotated simulations
• Debugging simulation miscompares and root-cause analysis
• Knowledge of scan chain insertion and DFT insertion flows
• Good understanding of MBIST
• Strong problem-solving and systematic debugging skills

Good to Have:

• Compression scan, LBIST, and advanced scan technologies
• JTAG 1149.1/1149.6, IEEE 1500, IEEE 1687
• Hands-on experience with Cadence DFT tools/flows
• Synthesis and Verilog testbench debugging