Senior Staff Engineer – DFT

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 4,500,000 - 7,000,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd is seeking a Senior Staff Engineer - DFT with deep hands-on expertise in DFT architecture, Scan Insertion, ATPG, and MBIST for complex ASIC/SoC designs. The role demands technical ownership of DFT implementation, coverage closure, pattern generation, and silicon signoff.

Key responsibilities include defining DFT methodologies, owning scan insertion and ATPG generation, developing MBIST architectures, and driving test-time optimization across RTL, Physical Design, and

Qualifications

• 10–15 years of hands-on experience in DFT/DFT implementation.
• Strong expertise in Scan Insertion, ATPG, MBIST, and Scan Compression.
• Hands-on experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, DFTMAX, Mentor Tessent.
• Deep knowledge of ATPG algorithms, fault models, test coverage, and pattern optimization.
• Experience with MBIST architecture, memory test algorithms, controllers, and diagnosis.

Responsibilities

• Define and implement DFT architecture and methodologies for complex SoCs.
• Own Scan insertion, scan compression, ATPG generation, and coverage closure.
• Develop and integrate MBIST architectures for embedded memories.
• Drive fault modeling, ATPG pattern generation, simulation, and pattern validation.
• Analyze and improve stuck-at, transition, bridging, and other structural fault coverage.

Skills

DFT architecture

Scan Insertion

ATPG

MBIST

Scan Compression

DFT signoff

Scripting Tcl

Python scripting

Tools

Synopsys TestMAX

TetraMAX

DFTMAX

Mentor Tessent

Job description

We are looking for a Senior Staff Engineer - DFT with deep hands-on expertise in DFT architecture, Scan Insertion, ATPG, and MBIST for complex ASIC/SoC designs. The role requires strong technical ownership across DFT implementation, coverage closure, pattern generation, and silicon signoff.

Key Responsibilities

• Define and implement DFT architecture and methodologies for complex SoCs.
• Own Scan insertion, scan compression, ATPG generation, and coverage closure.
• Develop and integrate MBIST architectures for embedded memories.
• Drive fault modeling, ATPG pattern generation, simulation, and pattern validation.
• Analyze and improve stuck-at, transition, bridging, and other structural fault coverage.
• Debug DFT/ATPG failures and drive coverage, pattern count, and test-time optimization.
• Collaborate with RTL, Physical Design, STA, Verification, and Product/Test Engineering teams.
• Drive DFT signoff, including DRC, coverage analysis, pattern validation, and production readiness.
• Develop and optimize DFT flows, scripts, and methodologies for improved automation and scalability.
• Provide technical leadership and mentorship across DFT projects.

Core Technical Requirements

• 10-15 years of hands-on experience in DFT / DFT implementation.
• Strong expertise in Scan Insertion, ATPG, MBIST, and Scan Compression.
• Hands-on experience with industry-standard DFT tools such as Synopsys TestMAX/TetraMAX, DFTMAX, Mentor Tessent, or equivalent.
• Strong understanding of ATPG algorithms, fault models, test coverage, test points, and pattern optimization.
• Deep knowledge of MBIST architecture, memory test algorithms, controllers, and diagnosis.
• Experience with DFT DRC, scan chain debugging, coverage closure, and ATPG simulation.
• Strong understanding of SoC DFT architecture, clock/reset handling, scan modes, compression, and test constraints.
• Experience with advanced-node ASIC/SoC designs and complex hierarchical DFT integration preferred.
• Strong scripting skills in Tcl, Python, Perl, or Shell.