Lead DFT Engineer

LanceSoft, Inc.; Bengaluru; On-site; INR 350,000 - 550,000; Full time

Job summary

LanceSoft, Inc. in Bengaluru is seeking an experienced Lead DFT Engineer to head DFT architecture, implementation, and verification for complex SoC designs.

You will drive scan insertion, ATPG pattern generation, coverage analysis, and MBIST validation, collaborating with RTL, PD, and verification teams to ensure production test readiness.

Qualifications

• 8+ years of hands-on DFT engineering experience.
• Strong expertise in ATPG and MBIST.
• Hands-on experience with Cadence DFT tools.
• Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.
• Strong debugging and cross-functional collaboration skills.

Responsibilities

• Lead DFT architecture, implementation, and verification for complex SoC designs.
• Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.
• Implement and verify MBIST, memory test architectures, and test controllers.
• Perform DFT rule checks, scan chain analysis, and test coverage optimization.
• Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
• Support DFT sign-off, test pattern validation, and production test readiness.

Skills

DFT engineering

ATPG

MBIST

Scan insertion

Test coverage analysis

Debugging

Cross-functional collaboration

Lead architect

Tools

Cadence DFT tools

Job description

We are looking for an experienced Lead DFT Engineer with strong expertise in Design-for-Test (DFT), ATPG, and MBIST, along with hands-on experience using Cadence tools.

Key Responsibilities

• Lead DFT architecture, implementation, and verification for complex SoC designs.
• Drive scan insertion, ATPG pattern generation, coverage analysis, and test pattern debugging.
• Implement and verify MBIST, memory test architectures, and test controllers.
• Perform DFT rule checks (DRC), scan chain analysis, and test coverage optimization.
• Collaborate with RTL, Physical Design, and Verification teams to resolve DFT-related issues.
• Support DFT sign-off, test pattern validation, and production test readiness.

Must-Have Skills

• 8+ years of hands-on DFT engineering experience.
• Strong expertise in ATPG and MBIST.
• Hands-on experience with Cadence DFT tools.
• Expertise in scan insertion, scan compression, DFT architecture, and test coverage analysis.
• Strong debugging, problem-solving, and cross-functional collaboration skills.

Preferred Skills

• Experience with full-chip SoC DFT implementation and silicon validation.
• Knowledge of JTAG, boundary scan, and IEEE 1500/1687 standards.
• Experience supporting DFT sign-off and manufacturing test requirements.