DFT Lead Engineer

Modernize Chip Solutions (MCS); Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Modernize Chip Solutions (MCS) is seeking an experienced DFT Engineer to lead DFT implementation, verification and sign-off for complex SoCs. You will drive ATPG/MBIST, scan chain insertion, and boundary-scan integration across multi-clock digital logic.

Collaboration with PHYs, IPs and Design teams is essential to ensure robust testability. Ideal candidates have 7–12 years of hands-on DFT in complex chips, with strong experience in Tessent flows and automotive or high-speed interfaces.

Qualifications

• 7–12 years of hands-on experience in DFT for complex SoCs.
• DFT architecture, insertion, verification and sign-off at full-chip level.
• Scan chain insertion and compression using Tessent across multi-clock digital logic.
• ATPG pattern generation, fault simulation and coverage analysis.
• MBIST for internal SRAMs, FIFOs and memory macros.
• DFT integration of PHYs and third-party IPs, including DFT boundary conditions and DFT port connectivity.
• BIST and bus isolation for PCS/PMA or similar high-speed interfaces.
• IEEE 1149.1 JTAG controllers and boundary scan.

Responsibilities

• DFT verification, coverage closure, pattern debugging and sign-off.
• Collaborate with Design, Verification and IP teams to resolve DFT issues.
• Support tape-out with robust DFT sign-off and boundary scan checks.
• Integrate DFT into PHYs and third‑party IPs and ensure testability.
• Develop and maintain DFT-related scripts for automation.

Skills

DFT implementation

ATPG and MBIST

DFT architecture

scan chain insertion

Tessent tooling

ATPG pattern generation

fault simulation

MBIST memory

DFT integration

boundary scan

JTAG controllers

test compression

clock reset handling

DFT verification

tape-out support

Tools

Tessent

Job description

• 7–12 years of hands‑on experience in DFT implementation, ATPG and MBIST for complex SoCs.
• Strong experience in DFT architecture, insertion, verification and sign‑off at full‑chip level.
• Experience with scan chain insertion and compression using Tessent across multi‑clock digital logic.
• Strong experience in ATPG pattern generation, fault simulation and coverage analysis.
• Hands‑on experience with MBIST for internal SRAMs, FIFOs and memory macros.
• Experience with DFT integration of PHYs and third‑party IPs, including DFT boundary conditions and DFT port connectivity.
• Experience with BIST and bus isolation, including PCS/PMA or similar high‑speed interface blocks.
• Experience integrating IEEE 1149.1 JTAG controllers and boundary scan.
• Good understanding of scan architecture, test modes, test compression, clock/reset handling and DFT constraints.
• Experience in DFT verification, coverage closure, pattern debugging and sign‑off.
• Design, Verification and IP teams to resolve DFT issues and support tape‑out.

Preferred

• Experience with Tessent DFT/ATPG/MBIST flows.
• Experience with automotive SoCs and ISO 26262‑related test requirements is an advantage.
• Experience with SerDes/PHY DFT integration is highly preferred.
• Good scripting skills in Tcl/Python/Perl for DFT automation.