Senior DFT Engineer

Onsemi; Bengaluru; On-site; INR 1,000,000 - 2,000,000; Full time

Job summary

Onsemi is looking for a DFT Engineer in Bengaluru, India. The role involves supporting design and implementation of DFT features for complex ASIC/SoC products, focusing on scan, ATPG, MBIST, and boundary scan. Candidates should have 3-5 years of experience in ASIC/SoC DFT and a strong understanding of DFT tools and fault models. A BS/MS in Electrical Engineering is required. The position offers a collaborative environment working with various engineering teams.

Qualifications

• 3–5 years of experience in ASIC / SoC DFT.
• Strong understanding of scan, ATPG, MBIST, and JTAG.
• Hands-on experience with DFT tools.

Responsibilities

• Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Implement and debug DFT logic to ensure high fault coverage.
• Generate and analyze ATPG patterns using industry-standard tools.

Skills

DFT Architectures

Scan

ATPG

MBIST

JTAG

Fault models

Education

BS/MS (B.Tech/M.Tech) in Electrical Engineering or related field

Tools

Synopsys DFT Compiler

TestKompress

Siemens Tessent

Job description

onsemi is seeking a DFT Engineer to support the design and implementation of Design‑for‑Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams.

Key Responsibilities

• Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG
• Implement and debug DFT logic to ensure high fault coverage and test quality
• Generate and analyze ATPG patterns using industry‑standard tools
• Support at‑speed and transition fault testing
• Collaborate with RTL, Physical Design, STA, and Test Engineering teams
• Address timing, CDC, and low‑power DFT considerations
• Support test coverage analysis, DFT signoff, and silicon bring‑up

Qualifications

• 3–5 years of experience in ASIC / SoC DFT
• Strong understanding of:
  • Scan, ATPG, MBIST, JTAG
  • Fault models: stuck‑at, transition, at‑speed
• Hands‑on experience with DFT tools such as:
  • Synopsys DFT Compiler / TestKompress
  • Siemens Tessent or equivalent
• Familiarity with timing, CDC, and low‑power DFT flows
• BS/MS (B.Tech/M.Tech) in Electrical Engineering or related field
• Experience with advanced nodes and large SoCs (Preferred)
• Exposure to physical‑aware DFT and test‑related ECOs (Preferred)
• Working knowledge of UPF and low‑power test strategies (Preferred)