Design Verification Engineer – Gate-Level Simulation (GLS)

Modernize Chip Solutions (MCS); Hyderabad; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Modernize Chip Solutions (MCS) in Hyderabad is seeking a Design Verification Engineer specialized in Gate-Level Simulation (GLS). You will contribute to DV workstreams, run GLS, debug, and analyze failures to ensure timing accuracy and functional correctness.

The ideal candidate has 4–5 years of DV experience, strong Verilog and SystemVerilog skills, and hands-on SDF timing annotation experience. You will collaborate with design teams to resolve complex issues and help bring GLS projects to

Qualifications

• 4–5 years of DV experience.
• Hands-on Gate-Level Simulation (GLS) expertise.
• Proficient in Verilog and SystemVerilog.
• Experience in sim, debugging, and failure analysis.
• Strong timing concepts and SDF annotation understanding.
• Excellent debugging and problem-solving skills.
• Worked on at least 3 GLS projects.

Skills

Design Verification

Gate-Level Simulation

Verilog

SystemVerilog

Timing Analysis

Debugging

Failure analysis

Tools

SDF Annotation

Job description

Job Title: Design Verification Engineer – Gate-Level Simulation (GLS)

Experience: 4–5 Years

Notice Period: Immediate to 15 Days Only

Mandatory Skills:

• Strong experience in Design Verification (DV).
• Hands‑on experience in Gate-Level Simulation (GLS).
• Strong knowledge of Verilog and SystemVerilog.
• Experience in simulation, debugging, and failure analysis.
• Good understanding of timing concepts and SDF annotation.
• Strong debugging and problem‑solving skills.
• Must have worked on a minimum of 3 GLS projects.