Digital Circuit Design Engineer

Lakshya Software Technologies Pvt. Ltd.; Hyderabad; On-site; INR 300,000 - 450,000; Full time

Job summary

Lakshya Software Technologies Pvt. Ltd. in Hyderabad seeks a Digital Circuit Design Engineer with 1–3 years of hands-on experience in digital circuit design. You will work on schematics, circuit simulations with SPICE, DC and transient analyses, and timing-related tasks. Strong communication to convey complex concepts is essential.

Experience with Verilog MOS switch-level models, netlist simulations, SDF back-annotation, and latch-based designs is valued. UVM familiarity is a plus for this role.

Qualifications

• 1 to 3 years of relevant experience in digital circuit design.
• Experience with schematics and circuit simulations using spice simulators.
• Perform DC and transient analyses.
• Ability to decipher circuit behavior from schematics.
• Familiarity with timing libraries, timing arcs, and related formats.
• Verilog MOS switch-level models and netlist simulations (zero delay, unit delay, path delay).
• Familiarity with static timing analysis.
• Gate-level simulations with SDF back annotation.
• Debug SDF annotation issues and ensure coverage.
• Hands-on with latch-based designs and timing requirements.
• Debug gate-level simulation failures and root causes.
• What-if analysis to validate fixes.
• SystemVerilog Assertions to specify expected behavior.
• UVM familiarity is a plus.
• Strong verbal and written communication for design peers.

Skills

Schematics

Circuit simulation

DC analysis

Transient analysis

Verilog MOS

Netlist simulation

SDF back-annotation

SystemVerilog Assertions

Latch-based timing

Gate-level simulation

Spice simulation

Timing libraries

Static timing analysis

Debugging

Communication skills

Tools

SDF back annotation

Verilog MOS models

Job description

Job Title : Digital Circuit Design Engineer

Experience: 1yrs to 3yrs.

schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.

? Experience in deciphering circuit behavior from schematics.

? Familiarity with circuit characterization, timing libraries - files and formats, timing arcs

? Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit

delay, and path delay simulations.

? Familiarity with static timing analysis

? Hands-on experience in Gate level simulations with SDF back annotation.

? Debug SDF annotation issues and ensure good annotation coverage.

? Hands-on experience with latch based designs and their timing requirements.

? Debugging Gate level simulation failures and root causing the failures to actual circuits.

Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.

? Hands-on knowhow of System Verilog Assertions to specify expected design behavior

? Familiarity with UVM is a plus

? Strong communication skills, with the ability to convey complex technical concepts to other

design peers in verbal and written form.

? Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor