Power VCD Simulation Engineer

Object Technology Solutions; India; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Object Technology Solutions is seeking a lead engineer to manage GLS activities across multiple projects. You will own GLS execution, timing validation and signoff readiness, while generating power VCDs/SAIFs and collaborating with design and verification teams to drive issue resolution.

The role requires strong SystemVerilog/UVM skills and scripting ability (Python/Tcl/Perl/Shell). You will develop GLS methodologies to improve quality and reduce turnaround times, and help ensure silicon

Responsibilities

• Lead and manage a team of engineers responsible for Gate-Level Simulation (GLS) activities across 1-2 projects.
• Own and drive overall functional GLS execution, timing validation and timing closure support, including setup, debug, triage, and signoff readiness.
• Generate and validate power VCDs/SAIFs for power analysis and collaborate with implementation teams on power optimization.
• Ensure timely execution, status reporting, risk identification, and escalation to meet project milestones and deliverables.
• Closely align with Design, Physical Design (PD), DFT, and Verification teams to resolve issues and drive closure.
• Develop GLS methodologies, automation, and best practices to improve quality, efficiency, and turnaround time.
• Support silicon readiness by identifying late-stage functional, timing, reset, clocking, and power-related issues before tapeout.
• Drive task prioritization, and execution tracking to ensure predictable delivery against project schedules.
• Gate-level simulation, timing validation/closure, power activity (VCD/SAIF) generation, debug, and signoff readiness, with solid understanding of Design, PD, DFT, and STA flows.
• Proficiency in SystemVerilog/UVM, scripting (Python/Tcl/Perl/Shell), debug tools, and methodology development to improve quality and execution efficiency.

Job description

Must have Skills:

• Lead and manage a team of 4 engineers responsible for Gate-Level Simulation (GLS) activities across 1-2 projects.


• Own and drive overall functional GLS execution, timing validation and timing closure support, including setup, debug, triage, and signoff readiness.


• Generate and validate power VCDs/SAIFs for power analysis and collaborate with implementation teams on power optimization.


• Ensure timely execution, status reporting, risk identification, and escalation to meet project milestones and deliverables.


• Closely align with Design, Physical Design (PD), DFT, and Verification teams to resolve issues and drive closure.


• Develop GLS methodologies, automation, and best practices to improve quality, efficiency, and turnaround time.


• Support silicon readiness by identifying late-stage functional, timing, reset, clocking, and power-related issues before tapeout.


• Drive task prioritization, and execution tracking to ensure predictable delivery against project schedules.


• Gate-level simulation, timing validation/closure, power activity (VCD/SAIF) generation, debug, and signoff readiness, with solid understanding of Design, PD, DFT, and STA flows.


• Proficiency in SystemVerilog/UVM, scripting (Python/Tcl/Perl/Shell), debug tools, and methodology development to improve quality and execution efficiency.