Semiconductor Design Engineer – Design Verification (DV)

Milieudigital Technologies India-Pvt. Ltd.; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Milieudigital Technologies India Pvt. Ltd. is seeking experienced Design Verification engineers to join its semiconductor team in Bengaluru. The role focuses on DV with hands-on circuit simulation, timing analysis, and gate-level verification across circuit, gate, and transistor levels.

Ideal candidates have 3–10 years in DV, experience with SPICE, DC and transient analyses, and GLS/SDF back-annotation. Proficiency in Verilog MOS models, netlists, and SVA/UVM is advantageous.

Qualifications

• 3–10 years of relevant experience in semiconductor design, design verification, or circuit-level verification.
• Hands-on experience with building-block and memory schematics.
• Strong knowledge of SPICE simulations, DC analysis, and transient analysis.
• Understanding of circuit characterization, timing libraries, timing arcs, and STA.
• Experience with Verilog MOS switch-level models and netlist simulations.
• Practical experience with gate-level simulation (GLS) and SDF back-annotation.
• Knowledge of latch-based designs and timing analysis.
• Ability to debug simulation failures and perform root-cause analysis.

Responsibilities

• Develop and analyze building-block and memory schematics.
• Perform SPICE circuit simulations, including DC and transient analysis.
• Understand circuit behavior and troubleshoot design-related issues.
• Perform circuit characterization and analyze timing libraries, timing arcs, and STA.
• Work with Verilog MOS switch-level models and netlist simulations.
• Execute gate-level simulations (GLS) with SDF back-annotation.
• Debug SDF annotation issues and ensure adequate annotation coverage.
• Analyze latch-based designs and verify timing requirements.
• Debug gate-level simulation failures and perform root-cause analysis at circuit, gate, or transistor level.
• Implement and validate fixes to improve simulation accuracy and design reliability.

Skills

Semiconductor DV

SPICE analysis

STA timing

GLS back-annotation

SVA basics

Education

B.E./B.Tech or M.E./M.Tech in ECE, Electrical, VLSI, Microelectronics or related

Tools

Verilog MOS models

Netlist simulations

SDF back-annotation

SystemVerilog

UVM knowledge

Job description

Company: Milieudigital Technologies India Pvt. Ltd.

Location: Hyderabad / Bangalore, India

Experience: 3–10 Years

Employment Type: Full-Time

Role Overview

Milieudigital Technologies India Pvt. Ltd. is looking for experienced Semiconductor Design Engineers specializing in Design Verification (DV) to join our semiconductor engineering team. The ideal candidate should have hands‑on experience in circuit simulation, timing analysis, gate‑level simulation, and debugging of semiconductor designs at circuit, gate, and transistor levels.

Key Responsibilities

• Develop and analyze building‑block and memory schematics.
• Perform SPICE circuit simulations, including DC and transient analysis.
• Understand circuit behavior and troubleshoot design‑related issues.
• Perform circuit characterization and analyze timing libraries, timing arcs, and Static Timing Analysis (STA).
• Work with Verilog MOS switch‑level models and netlist simulations using zero, unit, and path delays.
• Execute gate‑level simulations (GLS) with SDF back‑annotation.
• Debug SDF annotation issues and ensure adequate annotation coverage.
• Analyze latch‑based designs and verify timing requirements.
• Debug gate‑level simulation failures and perform root‑cause analysis at circuit, gate, or transistor level.
• Implement and validate fixes to improve simulation accuracy and design reliability.

Required Skills & Qualifications

• 3–10 years of relevant experience in semiconductor design, design verification, or circuit‑level verification.
• Hands‑on experience with building‑block and memory schematics.
• Strong knowledge of SPICE simulations, DC analysis, and transient analysis.
• Understanding of circuit characterization, timing libraries, timing arcs, and STA.
• Experience with Verilog MOS switch‑level models and netlist simulations.
• Practical experience with gate‑level simulation (GLS) and SDF back‑annotation.
• Knowledge of latch‑based designs and timing analysis.
• Ability to debug simulation failures and perform root‑cause analysis.
• Working knowledge of SystemVerilog Assertions (SVA); UVM knowledge is an added advantage.
• Strong analytical, communication, and problem‑solving skills.

Additional Expertise

• SPICE correlation and simulation debugging.
• Timing analysis and SDF annotation validation.
• Identifying and resolving issues at gate and transistor levels.
• Experience analyzing circuit behavior and implementing effective design fixes.

Interview Topics

• SPICE simulation, DC analysis, and transient analysis.
• Building‑block and memory schematic analysis.
• Circuit characterization, timing arcs, timing libraries, and STA.
• Verilog MOS switch‑level modeling and delay‑based simulations.
• Gate‑level simulation (GLS) and SDF back‑annotation.
• SDF annotation debugging and coverage.
• Latch‑based design and timing requirements.
• Root‑cause analysis of simulation failures.
• SystemVerilog Assertions (SVA) and basic UVM concepts.

Education

B.E. / B.Tech / M.E. / M.Tech in Electronics and Communication Engineering, Electrical Engineering, VLSI, Microelectronics, or a related discipline.