Design Verification Engineer

PQAngels Technologies Pvt. Ltd.; Bengaluru; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

PQAngels Technologies Pvt. Ltd. in Bengaluru seeks experienced Design Verification Engineers to work on challenging ASIC, SoC, and subsystem verification projects.

You will work with SystemVerilog and UVM to build verification environments and verify complex designs and high-speed interfaces. The role requires 5–11 years of hands-on DV experience, strong debugging skills, and a solid understanding of verification methodology.

Qualifications

• 5–11 years of relevant Design Verification experience.
• Strong hands-on SystemVerilog and UVM.
• Experience with Functional Coverage and SVA.
• Experience with high-speed interfaces (DDR/DDR4/DDR5/LPDDR, USB, Ethernet, NoC).
• Scripting knowledge in Python, Perl, and TCL.
• Good understanding of ASIC/VLSI verification methodology and flow.
• Strong debugging and root-cause analysis skills.

Responsibilities

• Develop and enhance SystemVerilog/UVM-based verification environments.
• Create verification plans, test strategies, test scenarios and test cases.
• Perform functional verification at IP, Subsystem and SoC levels.
• Develop reusable UVM components and verification infrastructure.
• Implement SystemVerilog Assertions (SVA).
• Analyze functional coverage and drive coverage closure.
• Execute simulations, regressions and debug failures.
• Verify high-speed protocols and interfaces.
• Support verification signoff and project closure.

Skills

SystemVerilog

UVM

Functional Coverage

SVA

Debugging

Root-cause analysis

High-speed interfaces

Python

Perl

TCL

Education

Bachelor/Master in ECE/EE/VLSI/Microelectronics

Job description

Experience: 5 -11 Years

Employment Type: Full-Time

About the Role

PQAngels Technologies is looking for experienced Design Verification Engineers to work on challenging ASIC, SoC, and Subsystem verification projects.

We are looking for engineers with strong hands-on expertise in SystemVerilog and UVM, along with experience verifying complex designs and high-speed interfaces.

What You Will Work On

• Develop and enhance SystemVerilog/UVM-based verification environments
• Create verification plans, test strategies, test scenarios and test cases
• Perform functional verification at IP, Subsystem and SoC levels
• Develop reusable UVM components and verification infrastructure
• Implement SystemVerilog Assertions (SVA)
• Analyze functional coverage and drive coverage closure
• Execute simulations, regressions and debug failures
• Perform RTL/testbench debugging and root-cause analysis
• Verify high-speed protocols and interfaces
• Support verification signoff and project closure
• Work closely with RTL, Architecture, Integration and other engineering teams
• Participate in technical reviews and customer discussions when required

Must-Have Skills

• 5-11 years of relevant Design Verification experience
• Strong hands-on SystemVerilog
• Strong hands-on UVM
• Experience with Functional Coverage
• Good experience in SVA
• Strong debugging and root-cause analysis skills
• Experience with one or more high-speed interfaces:
• DDR / DDR4 / DDR5 / LPDDR
• USB
• Ethernet
• NoC
• Scripting knowledge in Python / Perl / TCL
• Good understanding of ASIC/VLSI verification methodology and flow

Verification Tools

• Education: B.E./B.Tech/M.E./M.Tech in ECE, Electrical, Electronics, VLSI, Microelectronics or related fields.