Design Verification Engineer

VS TECHNOLOGIES; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

VS TECHNOLOGIES is hiring a Design Verification Engineer to advance semiconductor and VLSI verification efforts. The role involves building testbenches, developing verification components with SystemVerilog and UVM, and performing multi-level verification across blocks and systems.

You will analyze results, debug issues, and collaborate with RTL teams to close coverage gaps and improve methodologies. The position requires strong electronic design understandings, 4+ years of experience, and

Qualifications

• 4+ years of relevant experience in Design Verification.
• Strong knowledge of Digital Electronics and VLSI concepts.
• Hands-on experience with SystemVerilog.
• Good understanding of UVM methodology.

Responsibilities

• Create and maintain testbenches, test cases, and verification environments.
• Develop verification components using SystemVerilog and UVM.
• Perform functional, block-level, and system-level verification.
• Analyze simulation results and debug design/verification issues.
• Work closely with RTL design, architecture, and other engineering teams.
• Identify, track, and close functional and code coverage gaps.
• Perform regression testing and analyze failures.
• Contribute to improving verification methodologies and processes.
• Participate in design reviews, verification reviews, and project discussions.

Skills

SystemVerilog

UVM

Verification environments

DFD/RTL concepts

Functional coverage

Code coverage

Constrained-random verification

Simulation tools

Debugging

Problem solving

Tools

VCS

Questa

Xcelium

Job description

We are hiring Design Verification Engineers for our client, a leading product and service-based technology company. The opportunity is for professionals who are passionate about semiconductor and VLSI technologies and want to work on challenging design and verification projects.

Design Verification Engineer

About the Opportunity

We are hiring Design Verification Engineers for our client, a leading product and service-based technology company. The opportunity is for professionals who are passionate about semiconductor and VLSI technologies and want to work on challenging design and verification projects.

Responsibilities

• Develo
• Create and maintain testbenches, test cases, and verification environments.
• Develop verification components using SystemVerilog and UVM.
• Perform functional, block-level, and system-level verification.
• Analyze simulation results and debug design/verification issues.
• Work closely with RTL design, architecture, and other engineering teams.
• Identify, track, and close functional and code coverage gaps.
• Perform regression testing and analyze failures.
• Contribute to improving verification methodologies and processes.
• Participate in design reviews, verification reviews, and project discussions.

Required Skills

• Strong knowledge of Digital Electronics and VLSI concepts.
• Hands-on experience with SystemVerilog.
• Good understanding of UVM methodology.
• Experience in developing and debugging verification environments.
• Knowledge of functional coverage, code coverage, assertions, and constrained-random verification.
• Experience with simulation and debugging tools.
• Good understanding of RTL and digital design concepts.
• Strong analytical and problem-solving skills.

Preferred Skills

• Experience with AMBA protocols such as AXI, AHB, or APB.
• Knowledge of SVA (SystemVerilog Assertions).
• Experience with simulators such as VCS, Questa, or Xcelium.
• Exposure to scripting languages such as Python, Perl, or TCL.
• Experience working on SoC, IP, ASIC, or semiconductor projects.

Experience

4+ years of relevant experience in Design Verification.

Location

Bangalore | Chennai | Kochi | Pune

Employment Type

Full-time