Design Verification Engineer

Tessolve; Bengaluru; On-site; INR 900,000 - 1,700,000; Full time

Job summary

Tessolve Semiconductor is hiring experienced Design Verification Engineers with a strong background in IP and SoC-level verification, including processor/microarchitecture verification and high-speed interfaces such as PCIe, USB, and DDR. The role focuses on ownership of verification strategy, planning, and pre-silicon execution using industry-leading tools.

You will design SystemVerilog/UVM testbenches, directed and constrained-random tests, perform GLS with SDF back-annotation, and collaborate

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
• 5-30 years of experience in ASIC/IP/SoC/Processor Design Verification.
• Expertise in SystemVerilog, UVM, and constrained-random verification.
• Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi.
• Familiar with GLS verification (Gate-Level Simulation) and SDF back-annotation.
• Strong debugging skills and ability to read design specs and verification architecture.
• Proficient in scripting for test automation.

Responsibilities

• Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
• Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
• Write and maintain directed and constrained-random test cases.
• Perform GLS with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
• Verify processor cores or custom pipelines, including cache/memory subsystems and MMUs.
• Debug RTL and testbench issues using waveforms, logs, and assertions.
• Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
• Analyze functional/code/line/branch/coverage metrics and drive closure.
• Automate regressions and result analysis using scripting languages.
• Contribute to methodology improvements, tool evaluation, and reusable IP verification components.

Skills

SystemVerilog

UVM

Constrained-random

Scripting (Python/Perl/Shell/Tcl)

Verification planning

RTL debugging

Education

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering

Tools

VCS

Xcelium

Questa

Verdi

Job description

Experience: 5 to 30Years

Company: Tessolve Semiconductor

Job Type: Full-Time | Permanent

Job Summary:

Tessolve is hiring experienced Design Verification Engineers with a strong background in IP and SoC-level verification, along with specialization in one or more of the following areas: processor/microarchitecture verification, high-speed interfaces (e.g., PCIe, USB, DDR), or GLS (Gate-Level Simulation). This role involves ownership of verification strategy, planning, and execution in pre-silicon environments using industry-leading tools and methodologies.

Key Responsibilities:

• Develop and execute detailed verification plans for IP blocks, subsystems, or SoCs.
• Design and build SystemVerilog/UVM-based testbenches, scoreboards, monitors, and drivers.
• Write and maintain directed and constrained-random test cases.
• Perform GLS (Gate-Level Simulation) with SDF back-annotation, reset validation, scan chain checking, and X-propagation analysis.
• Verify processor cores or custom pipelines, including cache/memory subsystems, MMUs, and coherency.
• Debug RTL and testbench issues using waveforms, logs, and assertions.
• Collaborate with RTL, DFT, STA, firmware, and post-silicon teams to drive quality and coverage closure.
• Analyze functional/code/line/branch/coverage metrics and drive closure.
• Automate regressions and result analysis using scripting languages (Python, Perl, Shell, Tcl).
• Contribute to methodology improvements, tool evaluation, and reusable IP verification components.

Required Skills & Qualifications:

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
• 5-15 years of experience in ASIC/IP/SoC/Processor Design Verification.
• Expertise in SystemVerilog, UVM, and constrained-random verification.
• Hands-on experience with simulation tools: VCS, Xcelium, Questa, Verdi, etc.
• Proven track record in any one or more of the following:
• GLS Verification (Zero-delay and SDF annotated simulations, scan chain checks, X-handling)
• Strong debugging skills and understanding of design specs and verification architecture.
• Proficient in scripting (Python, Perl, Shell, or Tcl) for test automation.
• Familiar with DFT/scan concepts, low power (UPF), and assertion-based verification (SVA).

Good to Have:

• Experience in ARM-based SoCs or RISC-V CPU verification.
• Exposure to formal verification, LEC, or static verification tools.
• Knowledge of post-silicon validation, FPGA prototyping, or emulation.
• Experience leading small teams or mentoring junior engineers.