Design Engineer II

Cadence Design Systems; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cadence Design Systems is seeking an experienced professional to join the physical design team in Hyderabad. You will automate and maintain EDA flows, optimize PPA for IP cores, and drive efficient RTL-to-GDS workflows across multiple foundries.

The role requires hands-on design experience with Genus, Innovus and Fusion Compiler, strong scripting in Python and Tcl, and proven leadership and collaboration skills to deliver high-quality IP blocks on time.

Qualifications

• MS/MTech/BE/BTech in Electronics from reputed institutes.
• 2+ years of experience in ASIC physical design.
• Solid understanding of ASIC design flow: synthesis, physical design, timing and power analysis, formal verification.
• Experience with EDA tools Genus, Fusion Compiler.
• Strong leadership, communication and problem-solving skills.
• Scripting skills in Python and Tcl.

Responsibilities

• Develop, automate and maintain EDA flows and scripts for physical implementation.
• Develop TFM to optimize PPA for IPs and soft controllers.
• PPA characterization and optimization of flow for performance-oriented and power-oriented IP cores on multiple foundries.
• Manage regression infrastructure tracking RTL/flow quality and PPA of key designs.
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools.
• Develop automation scripts using AI tools to reduce design execution turnaround time.

Skills

Python scripting

Tcl scripting

Leadership

Communication

Analytical thinking

Team player

Education

MS/MTech/BE/BTech in Electronics

Tools

Genus

Innovus

Conformal

Litmus

Tempus

Voltus

Certus

Pegasus

Fusion Compiler

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Development, automation and maintenance of EDA flows and scripts for physical implementation
• Develop TFM to optimize PPA for IP’s and Soft Controllers
• PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
• Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
• Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
• Develop automation scripts using AI tools and reduce design execution turnaround time
• Required skills –
• Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years’ experience
• Physical design experience in ASIC design environment
• Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
• Prior experience in Logic Synthesis and PPA optimization techniques, Logic Equivalence Checks ( LEC ) debug experience for production designs
• A detailed understanding of synthesis flows, hands on experience in developing, debugging synthesis flows with EDA tools such as Genus, Fusion Compiler.
• Should have excellent leadership, communication, analytical and problem solving skills
• Solid scripting skills including Python and Tcl.
• Should be self-motivated and good team player.

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