Principal DFT Design Engineer

Cadence; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Cadence in Bengaluru seeks a professional to interact closely with cross-functional teams and mentor junior engineers. The ideal candidate has 7+ years of experience, a strong understanding of DFT concepts, and hands-on experience using industry-standard EDA tools such as Cadence Modus and Jasper.

This role emphasizes innovation and automation, requiring skills in scripting languages and debugging. Join Cadence to drive new DFT methodologies and improve quality and reliability in technology.

Qualifications

• 7+ years of relevant work experience.
• Strong understanding of DFT concepts.
• Experience with logic simulators from EDA vendors.

Responsibilities

• Interact with cross-functional teams on project deliverables.
• Mentor junior engineers.
• Drive innovation and automation.

Skills

DFT concepts

Communication skills

Hands-on experience with EDA Tools

Scripting languages (Perl/Tcl/Python)

Debugging skills

Education

BE/B.Tech/M.E/M.Tech

Tools

Cadence Modus

Jasper

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• This role requires close interaction with multiple cross‑functional teams across geographies to align on project receivables/deliverables.
• Mentoring junior engineers and driving innovation/automation.
• BE/B.Tech/M.E/M.Tech with 7+ years of relevant work experience and strong understanding of DFT concepts and good communication skills.
• Strong hands‑on experience using industry standard EDA Tools.
• Experience with logic simulators from one or more EDA vendors.
• Experience on industry standard ATPG tools like Cadence Modus.
• Experience with RTL lint tools like Jasper.
• Experience in scan insertion, coverage analysis and debugging skills on fault coverage enhancement is required.
• Programming in Perl/Tcl/Python or other scripting languages is a plus.
• Experience in post silicon validation, ATE debug and support is desired.
• Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
• Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in‑system test and debug capability.